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PDF R01DS0228EJ0060 Datasheet ( Hoja de datos )

Número de pieza R01DS0228EJ0060
Descripción 450MHz / 600MHz MCU
Fabricantes Renesas 
Logotipo Renesas Logotipo

Total 30 Páginas
		
R01DS0228EJ0060 Hoja de datos, Descripción, Manual
Preliminary Datasheet
Specifications in this document are tentative and subject to
RZ/T1 Group
R01DS0228EJ0060
Rev.0.60
Nov 14, 2014
450 MHz/600MHz, MCU with ARM Cortex®-R4F and -M3*1, on-chip FPU, 747/996 DMIPS, up to 1
Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed, CAN, various
communications interfaces such as an SPI multi-I/O bus controller, ∆Σ interface, safety functions,
encoder interfaces*1, and security functions*1
Features
On-chip 32-bit ARM Cortex-R4F processor
High-speed realtime control with maximum operating frequency of
450/600 MHz
Capable of 747/996 DMIPS (in operation at 450/600 MHz)
On-chip 32-bit ARM Cortex-R4F (revision r1p4)
Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
Instruction cache/data cache with ECC: 8 Kbytes per cache
High-speed interrupt
The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at single-
precision and double-precision.
Harvard architecture with 8-stage pipeline
Supports the memory protection unit (MPU)
ARM CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
(Oinn-pcrhoidpu3c2ts-biint cAoRrpMoCraotrintegxa-Mn3Rp-IrNoceensgsinoer )
150-MHz operating frequency
On-chip 32-bit ARM Cortex-M3 (revision r2p1)
RISC Harvard architecture with 3-stage pipeline
Supports the memory protection unit (MPU)
Low power consumption
Standby mode, sleep mode, and module stop function
On-chip extended SRAM
Up to 1 Mbyte of the on-chip extended SRAM with ECC
150 MHz
Data transfer
DMAC: 16 channels × 2 units
DMAC for the Ethernet controller: 1 channel
Event link controller
Module operations can be started by event signals rather than by
interrupt handlers.
Linked operation of modules is available even while the CPU is in
the sleep state.
Reset and power supply voltage control
Four reset sources including a pin reset
Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V
(internal)
Clock functions
External clock/oscillator input frequency: 25 MHz
CPU clock frequency: Up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Independent watchdog timer
Operated by a clock signal obtained by frequency-dividing the
clock signal from the low-speed on-chip oscillator: Up to 120 kHz
Safety functions
Register write protection, input clock oscillation stop detection,
CRC, IWDTa, and A/D self-diagnosis
An error control module is incorporated to generate a pin signal
output, interrupt, or internal reset in response to errors originating
in the various modules.
Security functions (optional)*2
Boot mode with security through encryption
Encoder interfaces (optional)*3
EnDat 2.2 and BiSS-compliant interfaces
PRBG0320GA-A 17×17mm, 0.8-mm pitch
PLQP0176LD-A 20 x 20mm, 0.4-mm pitch
Various communications interfaces
Ethernet
- EtherCAT slave controller: 2 ports (for products incorporating an
R-IN engine)
- Ether-MAC: 1 port (without the switching function)
or
- Ether-MAC: 1 port (2 ports with the switching function)
USB 2.0 high-speed host/function : 1 channel
CAN (compliant with ISO11898-1): 2 channels (max.)
SCIFA with 16-byte transmission and reception FIFOs: 5 channels
I2C bus interface: 2 channels for transfer at up to 400 kbps
RSPIa: 4 channels
SPIBSC: Provides a single interface for multi-I/O compatible
serial flash memory
External address space
Buses for high-speed data transfer at 75 MHz (max.)
Support for up to 6 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Up to 33 extended-function timers
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4
channels): Input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
Serial sound interface (1 channel)
■ ∆Σ interface
Up to 4 ΔΣ modulators are connectable externally.
12-bit A/D converters
12 bits × 2 units (max.)
(8 channels for unit 0; 16 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
Temperature sensor for measuring temperature
within the chip
General-purpose I/O ports
5-V tolerance, open drain, input pull-up
Multi-function pin controller
The locations of input/output functions for peripheral modules are
selectable from among multiple pins.
Operating temperature range
Tj = -40°C to +125°C
Note 1.
Note 2.
Note 3.
Optional
Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact our sales
representative.
For details, contact our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 1 of 51

1 page

R01DS0228EJ0060 pdf
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (4 / 7)
Classification
Timers
Module/Function
Description
General PWM timer
(GPTa)
16 bits × 4 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: software, and compare-match
Generation of triggers for A/D converter conversion
Digital noise filter function for signals on the input capture and external trigger pins
Event linking by the ELC
Programmable pulse
generator (PPG)
(4 bits × 4 groups) × 2 units*1
Pulse output with the MTU3a or TPUa output as a trigger
Maximum of 32 pulse-output possible
Compare match timer
(CMT)
(16 bits × 2 channels) × 3 units
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Event linking by the ELC
Compare match timer W
(CMTW)
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
Digital noise filter function for signals on the input capture pins
Event linking by the ELC
Watchdog timer (WDTA)
14 bits × 1 channel
Products incorporating an R-IN engine: 14 bits × 2 channels
Select from among six counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: Low-speed on-chip oscillator (LOCO)/2
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120
MHz)
Port output enable 3
(POE3)
Control of the high-impedance state of the MTU3a / GPTa's waveform output pins
4 pins for input from signal sources: POE0, POE4, POE8, POE10
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly
detection, or software
Additional programming of output control target pins is enabled
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 5 of 51

5 Page

R01DS0228EJ0060 arduino
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.3
List of Products (2 / 2)
Part No.
R7S910017CBG
Package
CPU
320 pins
Cortex-R4F
(PRBG0320GA
-A)
On-Chip
Extended
SRAM
Capacity
(1 MB for R-
IN Engine)
EtherCAT
Not
supported
Operating
Frequency
(max.)
600MHz
Security
Function
*1
Not
supported
Optional
Function
R-IN Engine
(CM3 :
150MHz)
R7S910117CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Available
R-IN Engine
(CM3 :
150MHz)
R7S910018CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Not
supported
Encoder I/F
R-IN Engine
(CM3 :
150MHz)
R7S910118CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Available
Encoder I/F
R-IN Engine
(CM3 :
150MHz)
Note: For the Encoder I/F and R-IN Engine, see the relevant documents of each product.
Note 1. Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact
our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 11 of 51

11 Page


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