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PDF R01DS0228EJ0060 Datasheet ( Hoja de datos )

Número de pieza R01DS0228EJ0060
Descripción 450MHz / 600MHz MCU
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R01DS0228EJ0060 datasheet

1 Page

R01DS0228EJ0060 pdf
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (4 / 7)
Classification
Timers
Module/Function
Description
General PWM timer
(GPTa)
16 bits × 4 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: software, and compare-match
Generation of triggers for A/D converter conversion
Digital noise filter function for signals on the input capture and external trigger pins
Event linking by the ELC
Programmable pulse
generator (PPG)
(4 bits × 4 groups) × 2 units*1
Pulse output with the MTU3a or TPUa output as a trigger
Maximum of 32 pulse-output possible
Compare match timer
(CMT)
(16 bits × 2 channels) × 3 units
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Event linking by the ELC
Compare match timer W
(CMTW)
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
Digital noise filter function for signals on the input capture pins
Event linking by the ELC
Watchdog timer (WDTA)
14 bits × 1 channel
Products incorporating an R-IN engine: 14 bits × 2 channels
Select from among six counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: Low-speed on-chip oscillator (LOCO)/2
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120
MHz)
Port output enable 3
(POE3)
Control of the high-impedance state of the MTU3a / GPTa's waveform output pins
4 pins for input from signal sources: POE0, POE4, POE8, POE10
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly
detection, or software
Additional programming of output control target pins is enabled
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 5 of 51

5 Page

R01DS0228EJ0060 arduino
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.3
List of Products (2 / 2)
Part No.
R7S910017CBG
Package
CPU
320 pins
Cortex-R4F
(PRBG0320GA
-A)
On-Chip
Extended
SRAM
Capacity
(1 MB for R-
IN Engine)
EtherCAT
Not
supported
Operating
Frequency
(max.)
600MHz
Security
Function
*1
Not
supported
Optional
Function
R-IN Engine
(CM3 :
150MHz)
R7S910117CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Available
R-IN Engine
(CM3 :
150MHz)
R7S910018CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Not
supported
Encoder I/F
R-IN Engine
(CM3 :
150MHz)
R7S910118CBG
320 pins
Cortex-R4F
(PRBG0320GA
-A)
(1 MB for R- Not
IN Engine) supported
600MHz
Available
Encoder I/F
R-IN Engine
(CM3 :
150MHz)
Note: For the Encoder I/F and R-IN Engine, see the relevant documents of each product.
Note 1. Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact
our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
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