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PDF W523S12 Data sheet ( Hoja de datos )
| Número de pieza | W523S12 | |
| Descripción | HIGH FIDELITY PowerSpeech | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W523SXX (PRELIMINARY)
HIGH FIDELITY PowerSpeechTM
GENERAL DESCRIPTION
The W523Sxx family are programmable speech synthesis ICs that utilize Winbond′s new high fidelity
voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide
powerful user-programmable functions that make this chip suitable for an extremely wide range of
speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration
shown below:
PART
NO.
W523S08 W523S10 W523S12 W523S15 W523S20 W523S25 W523S30
Duration
8 sec.
10 sec.
12 sec.
15 sec.
20 sec.
25 sec.
30 sec.
PART
NO.
Duration
W523S40
40 sec.
W523S50
50 sec.
W523S60
60 sec.
W523S70
70 sec.
W523S80
80 sec.
W523S99 W523M02
100 sec. 120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
• Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output
• New high fidelity synthesis algorithm
• Either PWM mode or D/A converter mode can be selected for AUD output
• Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs
• Two trigger input debounce times (50 mS or 400 uS) can be set
• Provides up to 2 LEDs and 5 STOP outputs
• Flexible functions programmable through the following:
− LD (Load), JP (Jump), MV (Move) and INC (Increase) commands
− Four general purpose registers: R0, R1, R2 and R3
− Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE
− Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6
− Speech equations
− END instruction
• Supports CPU interface operation
• Symbolic compiler supported
• Instruction cycle ≤ 400 µS typically
• Section control for
− Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000
- 1 - Revision A5
1 page  
W523SXX (PRELIMINARY)
2. MODE1 Register
BIT
7, 6, 1, 0
5
DESCRIPTION
X
LED Flash type
4 LED1 section
control
3 LED2 control
2 LED1 volume
control
DEFINITION
Don’ t care
1: Alternate
0: Synchronous
1: YES
0: NO
1: SECTION control
0: STPC control
1: OFF
0: ON
MODE1.5 is for LED flash type control. MODE1.4 is for LED1 section control ON/OFF. MODE1.3 is for
LED2 Section/STPC control. MODE1.2 is for LED1 volume control.
3. PAGE Register
BIT 7 6 5 4 3 2 1 0
PAGE - - - PG4 PG3 PG2 PG1 PG0
The bits 0 ~ 4 in PAGE register are used for page selection. Once the page mode being defined
(referring to the below section of “Option Control Function”), the working page is selected by the bits 0
~ 4 in the PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the
working page of the voice entry group. Not all of the bits 0 ~ 4 of PAGE register are used in different
page mode. They are listed as below table:
PAGE MODE PG4 PG3 PG2 PG1 PG0
1-page
8-page
16-page
32-page
×××××
××√√√
×√√√√
√√√√√
Where "×" means don′t care and "√" means must be set properly.
4. EN Register
BIT 7
EN0 X
6543
X TG2R TG1R X
2
X
EN1 X
X TG6R TG5R X
X
1
TG2F
TG6F
0
TG1F
TG5F
EN0 or EN1 is an 8-bit register that stores the rising/falling edge enable or disable status information
for all trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable,
Publication Release Date: Oct 2000
- 5 - Revision A5
5 Page 
W523SXX (PRELIMINARY)
Output Current of
STPA-STPE
Output Current of
SPK+, SPK-
IOL1
IOH1
IOL2
IOH2
VDD = 3V, Vout = 0.4V
VDD = 3V, Vout = 2.7V
VDD = 3V, Rl = 8Ω
0.8
-0.8
100
-100
mA
mA
mA
mA
AC CHARACTERISTICS
PARAMETER
Oscillation Frequency
(W58300 ICE chip)
Oscillation Frequency
(W523Sxx production
chip)
Oscillation Frequency
Deviation by Voltage
Drop
Instruction Cycle Time
POI Delay Time
Long Debounce Time
Short Debounce Time
SYM.
Fosc1
Fosc2
CONDITIONS
Ring oscillator, Rosc = 270 KΩ
Ring oscillator, Rosc = 560 KΩ
Ring Oscillator, Rosc = 1.2 MΩ
Ring Oscillator, Rosc = 2.4 MΩ
MIN.
2.7
1.3
2.7
1.3
TYP.
3
1.5
3
1.5
MAX.
3.3
1.7
3.3
1.7
UNIT
MHz
MHz
MHz
MHz
∆Fosc2
Fosc2
F(3V)-F(2.4V)
F(3V)
Tins
TPD
TDEBL
TDEBS
Fosc = 3 MHz, SR = 6 KHz
Fosc = 3 MHz
Fosc = 3 MHz, SR = 6 KHz
7.5 %
1/3
160
50
400
mS
mS
mS
µS
BONDING PAD DIAGRAM
19
1
2
3
4 5 6 7 8 9 10 11 12 13 14 15 16 17
18
- 11 -
Publication Release Date: Oct 2000
Revision A5
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet W523S12.PDF ] | |
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