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PDF ISL88731A Data sheet ( Hoja de datos )

Número de pieza ISL88731A
Descripción SMBus Level 2 Battery Charger
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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SMBus Level 2 Battery Charger
ISL88731A
The ISL88731A is a highly integrated Lithium-ion battery
charger controller, programmable over the SMBus system
management bus (SMBus). The ISL88731A is intended to be
used in a smart battery charger (SBC) within a smart battery
system (SBS) that throttles the charge power such that the
current from the AC-adapter is automatically limited. High
efficiency is achieved with a DC/DC synchronous-rectifier buck
converter, equipped with diode emulation for enhanced light
load efficiency and system bus boosting prevention. The
ISL88731A charges one to four Lithium-ion series cells, and
delivers up to 8A charge current. Integrated MOSFET drivers
and bootstrap diode result in fewer components and smaller
implementation area. Low offset current-sense amplifiers
provide high accuracy with 10mΩ sense resistors. The
ISL88731A provides 0.5% end-of-charge battery voltage
accuracy.
The ISL88731A provides a digital output that indicates the
presence of the AC-adapter as well as an analog output which
indicates the adapter current within 4% accuracy.
The ISL88731A is available in a small 5mmx5mm 28 Ld thin
(0.8mm) QFN package. An evaluation kit is available to reduce
design time. The ISL88731A is available in Pb-Free packages.
Pin Configuration
ISL88731A
(28 LD TQFN)
TOP VIEW
Features
• 0.5% Battery Voltage Accuracy
• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBus 2 Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
- Adapter Current (3% Accuracy)
- AC-Adapter Detection
• 11-Bit Battery Voltage Setting
• 6 Bit Charge Current/Adapter Current Setting
• 8A Maximum Battery Charger Current
• 11A Maximum Adapter Current
• +8V to +28V Adapter Voltage Range
• Pb-Free (RoHS compliant)
Applications
• Notebook Computers
• Tablet PCs
• Portable Equipment with Rechargeable Batteries
Ordering Information
28 27 26 25 24 23 22
NC 1
21 VDDP
ACIN 2
20 LGATE
VREF 3
19 PGND
ICOMP 4
NC 5
18 CSOP
17 CSON
VCOMP 6
NC 7
16 NC
15 VFB
8 9 10 11 12 13 14
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL88731AHRZ ISL887 31AHRZ -10 to +100 28 Ld 5x5 TQFN L28.5x5B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL88731A. For more information on MSL please see
techbrief TB363.
June 8, 2011
FN6738.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL88731A pdf
ISL88731A
Electrical Specifications DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V,
CVDDP = 1µF, IVDDP = 0mA, TA = -10°C to +100°C. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued)
PARAMETER
CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
BOOT Supply Current
UGATE High
170 290 400 µA
PHASE Input Bias Current
UGATE ON-Resistance Low
UGATE ON-Resistance High
LGATE ON-Resistance High
LGATE ON-Resistance Low
Dead Time
VDCON = 28V, VCSON = VPHASE = 20V
IUGATE = -100mA
IUGATE = 10mA
ILGATE = +10mA
ILGATE = -100mA
Falling UGATE to rising LGATE or
falling LGATE to rising UGATE
0 2 µA
0.9 1.6 Ω
1.4 2.5 Ω
1.4 2.5 Ω
0.9 1.6 Ω
35 50 80 ns
ERROR AMPLIFIERS
GMV Amplifier Transconductance
200 250 300 µA/V
GMI Amplifier Transconductance
40 50 60 µA/V
GMS Amplifier Transconductance
40 50 60 µA/V
GMI/GMS Saturation Current
15 21 25 µA
GMV Saturation Current
10 17 30 µA
ICOMP, VCOMP Clamp Voltage
LOGIC LEVELS
0.25V < VICOMP, VCOMP < 3.5V
200 300 400 mV
SDA/SCL Input Low Voltage
VDDSMB = 2.7V to 5.5V
0.8 V
SDA/SCL Input High Voltage
VDDSMB = 2.7V to 5.5V
2V
SDA/SCL Input Bias Current
VDDSMB = 2.7V to 5.5V
-1 1 µA
SDA, Output Sink Current
VSDA = 0.4V
7 15
mA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SMBus Timing Specification VDDSMB = 2.7V TO 5.5V
PARAMETERS
SYMBOL
SMBus Frequency
FSMB
Bus Free Time
TBUF
Start Condition Hold Time from SCL
THD:STA
Start Condition Setup Time from SCL
TSU:STA
Stop Condition Setup Time from SCL
TSU:STO
SDA Hold Time from SCL
THD:DAT
SDA Setup Time from SCL
TSU:DAT
SCL Low Timeout (Note 7)
TTIMEOUT
SCL Low Period
TLOW
SCL High Period
THIGH
Maximum Charging Period Without a SMBus Write to
ChargeVoltage or ChargeCurrent Register
NOTES:
7. If SCL is low for longer than the specified time, the charger is disabled.
CONDITIONS
MIN TYP MAX UNITS
10 100 kHz
4.7 µs
4 µs
4.7 µs
4 µs
300 ns
250 ns
22 25 30 ms
4.7 µs
4 µs
140 180 220
s
5 FN6738.3
June 8, 2011

5 Page





ISL88731A arduino
ISL88731A
The System Management Bus
The System Management Bus (SMBus) is a 2-wire bus that
supports bidirectional communications. The protocol is described
briefly here. More detail is available from www.smbus.org.
General SMBus Architecture
VDDSMB
SMBUS MASTER
INPUT
SCL
CONTROL OUTPUT
CPU
INPUT
SDA
CONTROLOUTPUT
SMBUS SLAVE
INPUT
SCL
OUTPUTCONTROL
INPUT
SDA
OUTPUTCONTROL
STATE
MACHINE,
REGISTERS,
MEMORY,
ETC
SMBUS SLAVE
INPUT
SCL
OUTPUT CONTROL
INPUT
SDA
OUTPUT CONTROL
STATE
MACHINE,
REGISTERS,
MEMORY,
ETC
TOOTHER
SLAVE DEVICES
Data Validity
The data on the SDA line must be stable during the HIGH period
of the SCL, unless generating a START or STOP condition. The
HIGH or LOW state of the data line can only change when the
clock signal on the SCL line is LOW. Refer to Figure 16.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 16. DATA VALIDITY
START and STOP Conditions
As shown in Figure 17, START condition is a HIGH-to-LOW transition
of the SDA line while SCL is HIGH.
The STOP condition is a LOW-to-HIGH transition on the SDA line
while SCL is HIGH. A STOP condition must be sent before each
START condition.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 17. START AND STOP WAVEFORMS
Acknowledge
Each address and data transmission uses 9-clock pulses. The ninth
pulse is the acknowledge bit (ACK). After the start condition, the
master sends 7-slave address bits and a R/W bit during the next 8-
clock pulses. During the ninth clock pulse, the device that recognizes
its own address holds the data line low to acknowledge. The
acknowledge bit is also used by both the master and the slave to
acknowledge receipt of register addresses and data (see Figure 18).
SCL
SDA
START
1
MSB
2
89
ACKNOWLEDGE
FROM SLAVE
FIGURE 18. ACKNOWLEDGE ON THE I2C BUS
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address (0001001 for the ISL88731A)
followed by the R/W bit. The R/W bit is 0 for a write or 1 for a read. If
any slave devices on the SMBus bus recognize their address, they
will Acknowledge by pulling the serial data (SDA) line low for the last
clock cycle in the control byte. If no slaves exist at that address or
are not ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition.
Once the control byte is sent, and the ISL88731A acknowledges
it, the 2nd byte sent by the master must be a register address
byte such as 0x14 for the ChargeCurrent register. The register
address byte tells the ISL88731A which register the master will
write or read. See Table 1 for details of the registers. Once the
ISL88731A receives a register address byte it responds with an
acknowledge.
11 FN6738.3
June 8, 2011

11 Page







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