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PDF TC74VHC393FK Data sheet ( Hoja de datos )

Número de pieza TC74VHC393FK
Descripción Dual Binary Counter
Fabricantes Toshiba 
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TC74VHC393F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC393F,TC74VHC393FT,TC74VHC393FK
Dual Binary Counter
The TC74VHC393 is an advanced high speed CMOS 4-BIT
BINARY COUNTER fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
It contains two independent counter circuits in one package, so
that counting or frequency division of eight binary bits can be
achieved with one IC.
This device changes state on the negative going transition of
the CLOCK pulse. The counter can be reset to “0” (QA to QD =
“L”) by a high at the CLEAR input regardless of other inputs.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: fmax = 170 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Low noise: VOLP = 0.8 V (max)
Pin and function compatible with 74ALS393
TC74VHC393F
TC74VHC393FT
TC74VHC393FK
Weight
SOP14-P-300-1.27A
TSSOP14-P-0044-0.65A
VSSOP14-P-0030-0.50
: 0.18 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2012-02-29

1 page




TC74VHC393FK pdf
TC74VHC393F/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Symbol
Propagation delay
time
( CK -QA)
Propagation delay
time
( CK -QB)
Propagation delay
time
( CK -QC)
Propagation delay
time
( CK -QD)
Propagation delay
time
(CLR-Qn)
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpHL
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
fmax
CIN
CPD
Test Condition
Ta = 25°C
VCC (V) CL (pF) Min Typ. Max
3.3 ± 0.3
15
8.6 13.2
50 11.1 16.7
15 5.8 8.5
5.0 ± 0.5
50 7.3 10.5
15 10.2 15.8
3.3 ± 0.3
50 12.7 19.3
15 6.8 9.8
5.0 ± 0.5
50 8.3 11.8
15 11.7 18.0
3.3 ± 0.3
50 14.2 21.5
15 7.7 11.2
5.0 ± 0.5
50 9.2 13.2
15 13.0 19.7
3.3 ± 0.3
50 15.5 23.2
15 8.5 12.5
5.0 ± 0.5
50 10.0 14.5
15 7.9 12.3
3.3 ± 0.3
50 10.4 15.8
15 5.4 8.1
5.0 ± 0.5
50 6.9 10.1
15 75 120
3.3 ± 0.3
50 45 65
15
125 170
5.0 ± 0.5
50 85 115
― ― 4 10
(Note) 23
Ta =
40 to 85°C
Min Max
1.0 15.5
1.0 19.0
1.0 10.0
1.0 12.0
1.0 18.5
1.0 22.0
1.0 11.5
1.0 13.5
1.0 21.0
1.0 24.5
1.0 13.0
1.0 15.0
1.0 23.0
1.0 26.5
1.0 14.5
1.0 16.5
1.0 14.5
1.0 18.0
1.0 9.5
1.0 11.5
65
35
105
75
10
――
Unit
ns
ns
ns
ns
ns
MHz
pF
pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD · VCC · fIN + ICC / 2 (per counter)
5 2012-02-29

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