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PDF NAND08GW3B2A Data sheet ( Hoja de datos )

Número de pieza NAND08GW3B2A
Descripción NAND Flash Memories
Fabricantes Numonyx 
Logotipo Numonyx Logotipo



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NAND04GW3B2B
NAND08GW3B2A
4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page
3V, NAND Flash Memories
Features
High density NAND Flash Memory
– up to 8 Gbit memory array
– Up to 256 Mbit spare area
– Cost effective solution for mass storage
applications
NAND Interface
– x8 bus width
– Multiplexed Address/ Data
Supply voltage
– 3.0V device: VDD = 2.7 to 3.6V
Page size
– (2048 + 64 spare) Bytes
Block size
– (128K + 4K spare) Bytes
Page Read/Program
– Random access: 25µs (max)
– Sequential access: 30ns (min)
– Page program time: 200µs (typ)
Copy Back Program mode
– Fast page copy without external buffering
Cache Program and Cache Read modes
– Internal Cache Register to improve the
program and read throughputs
Fast Block Erase
– Block erase time: 2ms (typ)
Status Register
Electronic Signature
Chip Enable ‘don’t care’
– for simple interface with microcontroller
Serial Number option
TSOP48 12 x 20mm
Data protection
– Hardware and Software Block Locking
– Hardware Program/Erase locked during
Power transitions
Data integrity
– 100,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
ECOPACK® package
Development tools
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– File System OS Native reference software
– Hardware simulation models
December 2007
Rev 5
1/58
www.numonyx.com
1

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NAND08GW3B2A pdf
NAND04GW3B2B, NAND08GW3B2A
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Copy Back Program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC Characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 55
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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NAND08GW3B2A arduino
NAND04GW3B2B, NAND08GW3B2A
2 Memory array organization
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
The pages are split into a 2048 Byte main area and a spare area of 64 Bytes. Refer to
Figure 4: Memory Array Organization.
2.1
Bad Blocks
The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block
Management for more details).
Table 3 shows the minimum number of valid blocks. The values shown include both the Bad
Blocks that are present when the device is shipped and the Bad Blocks that could develop
later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to Section 8: Software algorithms).
Table 3. Valid Blocks
Density of Device
Min
4 Gbits
8 Gbits(1)
4016
8032
1. The NAND08GW3B2A is composed of two 4 Gbit dice.
Max
4096
8192
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