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PDF CLAA140WA01A Data sheet ( Hoja de datos )
| Número de pieza | CLAA140WA01A | |
| Descripción | Display Module | |
| Fabricantes | CHUNGHWA PICTURE TUBES | |
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Chunghwa Picture Tubes, Ltd.
Technical Specification
To : SCL
Date : 2011/06/16
TFT LCD
CLAA140WA01A
ACCEPTED BY:
APPROVED BY
Ronald Huang
CHECKED BY
Neptune Kang
PREPARED BY
Carol Shen
Prepared by : TFT-LCD Product Planning Management Division
CHUNGHWA PICTUER TUBES, LTD.
1127 Hopin Rd., Padeh, Taoyuan, Taiwan 334, R.O.C.
TEL: +886-3-3675151 FAX: +886-3-377-3003
Doc.No:
CLAA140WA01A-SCL-V1-2011/06/16
T- 3650002- 000- A NEW
Issue Date: 2011/06/16
1 page  
CPT
CHUNGHWA PICTURES TUBES, LTD.,
3. ELECTRICAL CHARACTERISTICS
(1)TFT-LCD
Ta = 25°C
ITEM
SYMBOL MIN TYP MAX UNIT Remark
Power Supply Voltage for LCD
VCC
3.0
3.3
3.6
V
Power Supply Current for LCD*1) ICC - 340 360 mA
ICC Rush Current*2)
IRUSH
0.5 A
Input Voltage
VIN 0
-
VCC
V
Logic Common Mode Voltage VCM 1.125 1.25 1.375
V
input
Voltage
Differential Input Voltage
Threshold Voltage(High)
|VID|
VTH
250
-
350
-
450
100
mV
mV
When
Threshold Voltage(Low) VTL
-100
-
- mV VCM = + 1 2V
Tolerance of VID
ΔVID
-
- 35 mV
Tolerance of VCM
ΔVCM
-
- 35 mV
[Note]：*1)Power Supply Current is in Gray-128 pattern and operation
frequency is 68.25MHz.
*2)Vcc rise time is 520μsec
[Note 1]
VCC=3.3V
VCC turn on conditions :
t1≦10ms
1 sec≦t5
0.01 ms＜t2≦50 ms
0.01 ms＜t3≦50 ms
300 ms≦t6
300 ms≦t7
0.01 ms＜t4≦10 ms
3.0V
LCD Power Supply
Logic Signal
0.3V
t1 t2
V in = 3 .3 V
data
3.0V
0.3V
0.3V
t3 t4
t5
VL
Backlight Power Supply
t6 t7
Data: RGB DATA, DCLK, HD, VD, DENA
VCC dip conditions :
1) When 2.7V≦VCC<3.0V, td≦10 ms
2) When VCC<2.7V
VCC dip conditions should follow VCC turn on conditions.
Vin=3.3V
CPT Confidential
td
4/19 CLAA140WA01A-SCL-V1-2011/06/16
5 Page 
CPT
CHUNGHWA PICTURES TUBES, LTD.,
(3)Timing Specifications
ITEM
SYMBOL
CLK frequency
fCLKin
CLK period
tCLKin
LVDS High to Low transition time
LLHT
LVDS Low to High transition time
LHLT
LVDS Strobe position of Bit 0
Input Strobe position of Bit 1
Rspos0
Rspos1
Timing Strobe position of Bit 2
Rspos2
Strobe position of Bit 3 f = 68.9MHz Rspos3
Strobe position of Bit 4
Rspos4
Strobe position of Bit 5
Rspos5
Strobe position of Bit 6
Rspos6
MIN
57.95
12.76
-
-
0.7
2.9
5.1
7.3
9.5
11.7
13.9
TYP
68.25
14.65
0.75
0.75
1.1
3.3
5.5
7.7
9.9
12.1
14.3
MAX
78.39
17.26
1.5
1.5
1.4
3.6
5.8
8.0
10.2
12.4
14.6
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Total
tH 1344 1440 1500 tCLK
LCD input
signal
Horizonta
Active
Blank
tHA 1280 1280 1280 tCLK
tHB 64 160 220 tCLK
( LVDS
Tx Input ,
Rx output )
DENA
Vertical
Frame Rate
Tatol
Active
fV
tV
tVA
55 60 65 Hz
784 790 804
tH
768 768 768
tH
Blank
tVB 16 22 36 tH
[Note]
1) Data is latched at fall edge of DCLK in this specification.
2) DENA (Data Enable) should always be positive polarity as shown in the timing
specification.
3) CLKIN should appear during all invalid period.
CPT Confidential
10/19
CLAA140WA01A-SCL-V1-2011/06/16
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CLAA140WA01A.PDF ] | |
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