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PDF LC470EUE-SEM2 Data sheet ( Hoja de datos )
| Número de pieza | LC470EUE-SEM2 | |
| Descripción | Display Module | |
| Fabricantes | LG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LC470EUE-SEM2 (archivo pdf) en la parte inferior de esta página. Total 35 Páginas | ||
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Ver. 0.2
Product Specification
CONTENTS
COVER
ITEM
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
INTERFACE CONNECTIONS
SIGNAL TIMING SPECIFICATIONS
LVDS SIGNAL SPECIFICATIONS
COLOR DATA REFERENCE
POWER SEQUENCE
OPTICAL SPECIFICATIONS
MECHANICAL CHARACTERISTICS
RELIABILITY
INTERNATIONAL STANDARDS
SAFETY
EMC
Environment
PACKING
INFORMATION OF LCM LABEL
PACKING FORM
PRECAUTIONS
MOUNTING PRECAUTIONS
OPERATING PRECAUTIONS
ELECTROSTATIC DISCHARGE CONTROL
PRECAUTIONS FOR STRONG LIGHT EXPOSURE
STORAGE
HANDLING PRECAUTIONS FOR PROTECTION FILM
LC470EUE
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1 page  
Product Specification
LC470EUE
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight .
Table 2. ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Circuit :
Power Input Voltage
VLCD
Power Input Current
ILCD
Power Consumption
Rush current
PLCD
IRUSH
Min
10.8
-
-
-
Value
Typ
12.0
537
790
6.4
-
Max
13.2
698
1027
8.4
3.0
Unit
VDC
mA
mA
Watt
A
Note
1
2
1
3
Note
1. The specified current and power consumption are under the VLCD=12.0V, Ta=25 ± 2C, fV=60Hz
condition , and mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under 5% of typical voltage
White : 255 Gray
Black : 0 Gray
Ver. 0.2
Mosaic Pattern(8 x 6)
5 /35
5 Page 
Product Specification
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LC470EUE
LVDS +
# V CM = {( LVDS +) + ( LVDS - )} /2
0V
Description
Symbol
Min
LVDS Common mode Voltage
LVDS Input Voltage Range
Change in common mode Voltage
VCM
VIN
VCM
1.0
0.7
-
2) AC Specification
Tclk
V CM
V IN _ MAX V IN _ MIN
Max Unit
1.5 V
1.8 V
250 mV
Note
-
-
-
LVDS Clock
LVDS Data
A
LVDS 1st Clock
LVDS 2nd / 3rd / 4th Clock
t tSKEW SKEW
tSKEW_min tSKEW_max
( Fclk = 1 /Tclk )
Tclk
A
80%
20%
tRF
Description
Symbol Min
Max Unit
LVDS Differential Voltage
High Threshold
VTH
100
600
mV
Low Threshold VTL -600 -100 mV
LVDS Clock to Data Skew
tSKEW
- |(0.2*Tclk)/7| ps
LVDS Clock/DATA Rising/Falling time
tRF 260 |(0.3*Tclk)/7| ps
Effective time of LVDS
teff |360|
-
ps
LVDS Clock to Clock Skew (Even to Odd)
tSKEW_EO
-
|1/7* Tclk|
ps
Note 1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If tRF isnt enough, teff should be meet the range.
3. LVDS Differential Voltage is defined within teff
Ver. 0.2
Note
3
-
2
-
-
11 /35
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet LC470EUE-SEM2.PDF ] | |
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