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PDF Hi3518 Data sheet ( Hoja de datos )
| Número de pieza | Hi3518 | |
| Descripción | Hardware Design User Guide | |
| Fabricantes | Hisilicon | |
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 1. - Hardware Design User Guide  Hay una vista previa y un enlace de descarga de Hi3518 (archivo pdf) en la parte inferior de esta página. Total 38 Páginas | ||
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Hi3518 Hardware Design
User Guide
Issue
Date
01
2013-06-30
1 page  
Hi3518 Hardware Design
User Guide
About This Document
Issue 00B03 (2012-11-25)
This issue is the third draft release, which incorporates the following changes:
Chapter 2 PCB Design Recommendations
In section 2.1.1, Figure 2-2 and related descriptions are added.
Issue 00B02 (2012-10-30)
This issue is the second draft release, which incorporates the following changes:
Chapter 1 Design Recommendations for Schematic Diagrams
Figure 1-1 is updated.
In sections 1.1.3, 1.1.5.3, 1.2.1, 1.2.2, 1.3.2, 1.3.3, and 1.4, the descriptions are updated.
Section 1.2.5 "Power-on and Power-off Sequences" is added.
Chapter 2 PCB Design Recommendations
In sections 2.1.1, 2.1.3, 2.1.4, 2.1.5, 2.2.1, 2.2.2.1, and 2.2.2.2, the descriptions are updated.
The section "I/O Power" is added.
Chapter 3 Heat Design Recommendations
Table 3-1 and Table 3-2 are updated.
In section 3.2.1, the low-power configurations for idle modules in the schematic diagram are
updated.
Issue 00B01 (2012-08-30)
This issue is the first draft release.
Issue 01 (2013-06-30)
HiSilicon Proprietary and Confidential
Copyright © HiSilicon Technologies Co., Ltd
iii
5 Page 
1 Design Recommendations for Schematic Diagrams
Hi3518 Hardware Design
User Guide
1.1.2 Reset and Watchdog Circuit
The Hi3518 selects the internal or external reset mode by checking the status of the POR_SEL
pin during power-on:
The Hi3518A supports various reset modes, whereas the Hi3518C supports only internal reset.
z When the POR_SEL level is low, internal reset is selected. After the master chip is
powered on, the power-on-reset (POR) circuit resets the entire chip (the pulse width of
the reset signal is about 140 ms), and the RSTN pin is invalid.
When internal reset is selected, the RSTN and WDG_RSTN pins can be floated. In this
case, peripherals (such as the flash memory) must be reset before the system is reset or
peripherals and the system are reset at the same time. Otherwise, the system cannot boot.
In addition, when internal reset is selected and the WDG_RSTN pin is floated, the
watchdog generates a reset signal in the chip to reset the system, and the
SYS_RSTN_OUT pin outputs a reset signal to reset peripherals. You are advised to
output the reset signal by using the SYS_RSTN_OUT pin of the Hi3518 to reset
peripherals. The SYS_RSTN_OUT pin of the Hi3518A or Hi3518C_BGA is located in
V18. The Hi3518C_QFP supports only internal reset, and its SYS_RSTN_OUT pin is
pin 82.
z When the POR_SEL level is high, external reset is selected. In this case, the RSTN pin is
a reset signal input pin. The valid reset signal must have low-level pulse, and the pulse
width must be greater than 12 input clock cycles for the XIN pin. Typically, the pulse
width of the reset signal is 100–300 ms.
During board design, if external reset is selected, you are advised to use a dedicated reset
chip to generate a reset signal to ensure system stability.
When an exception occurs in the system, the WDG_RSTN pin can generate a low-level
pulse. The pulse triggers an external reset chip to generate a reset signal. The
WDG_RSTN pin cannot directly connect to the RSTN pin.
As the WDG_RSTN pin is an open drain (OD) output pin, it must connect to an external
pull-up resistor. A 4.7 kΩ resistor is recommended.
Figure 1-2 shows the typical external reset and watchdog circuit.
2
HiSilicon Proprietary and Confidential
Copyright © HiSilicon Technologies Co., Ltd
Issue 01 (2013-06-30)
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet Hi3518.PDF ] | |
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