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PDF 12NK90Z Data sheet ( Hoja de datos )

Número de pieza 12NK90Z
Descripción STW12NK90Z
Fabricantes STMicroelectronics 
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No Preview Available ! 12NK90Z Hoja de datos, Descripción, Manual

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STW12NK90Z
N-channel 900V - 0.72- 11A - TO-247
Zener-protected SuperMESH™ Power MOSFET
General features
Type
STW12NK90Z
VDSS
900V
RDS(on)
<0.88
ID pW
11A 230W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
TO-247
Internal schematic diagram
Order codes
Part number
STW12NK90Z
Marking
W12NK90Z
Package
TO-247
Packaging
Tube
October 2006
Rev 5
1/14
www.st.com
14

1 page




12NK90Z pdf
STW12NK90Z
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Drain-source
V(BR)DSS breakdown voltage
IDSS
Zero gate voltage
drain current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate-body leakage
current (VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
Min.
ID = 1mA, VGS =0
VDS = max rating
VDS = max rating,
TC = 125°C
VGS = ± 20V
VDS = VGS, ID = 100µA
VGS = 10V, ID = 5.5A
900
3
Typ. Max. Unit
V
1 µA
50 µA
±10
3.75 4.5
0.72 0.88
µA
V
Table 6.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Forward
transconductance
VDS = 15V, ID = 5.5A
11 S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25V, f = 1MHz,
VGS = 0
3500
280
58
pF
pF
pF
Coss
(2)
eq
Equivalent output
capacitance
VGS = 0V, VDS = 0V
to 800V
117 pF
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 450V, ID = 5A
RG = 4.7VGS = 10V
(see Figure 13)
VDD = 720V, ID = 10A,
VGS = 10V, RG = 4.7
(see Figure 14)
31 ns
20 ns
88 ns
55 ns
113 152 nC
19 nC
60 nC
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
5/14

5 Page





12NK90Z arduino
STW12NK90Z
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/14

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