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PDF HCF4015B Data sheet ( Hoja de datos )
| Número de pieza | HCF4015B | |
| Descripción | DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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HCC/HCF4015B
DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL
INPUT/PARALLEL OUTPUT
. MEDIUM SPEED OPERATION : 12MHz (typ.)
CLOCK RATE AT VDD - VSS = 10V
. FULLY STATIC OPERATION
. 8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT
AND OUTPUT BUFFERING
. HIGH NOISE IMMUNITY
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD NO. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY F
(Plastic Package) (Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC4015BF HCF4015BM1
HCF4015BEY HCF4015BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4015B (extended temperature range) and
HCF4015B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package and plastic
micropackage.
The HCC/HCF4015B consists of two identical, inde-
pendent, 4-stage serial-input/parallel-output registers.
Each register has independent CLOCK and RESET
inputs as well as a single serial DATA input. ”Q” out-
puts are available from each of the four stages on both
registers. All register stages are D-type, master-slave
flip-flops. The logic level present at the DATA input is
transferred into the first register stage and shifted over
one stage at each positive-going clock transition. Re-
setting of all stages is accomplished by a high level on
the reset line. Register expansion to 8 stages using
one HCC/HCF4015B package, or to more than 8
stages using additional HCC/HCF4015B’s is possible.
June 1989
1/12
1 page  
HCC/HCF4015B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 °C, CL = 50 pF, RL = 200 kΩ,
typical temperature coefficient for all VDD values is 0.3 %/°C, all input rise and fall times = 20 ns)
Symbol
Parameter
CLOCKED OPERATION
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
Unit
tP L H, tP HL Propagation Delay Time
(carry out or decoded out lines)
5 160 320
10 80 160 ns
15 60 120
t THL , tT L H Transition Time
(carry out or decoded out lines)
fCL Maximum Clock Input Frequency
5 100 200
10
50 100
ns
15 40 80
5 36
10 6 12
MHz
tW Clock Pulse Width
15 8.5 17
5 180 90
10 80 40
ns
15 50 25
t r, tf* Clock Input Rise or Fall Time
5 15
10 15 µs
t se tu p Data Setup Time
15 15
5 70 35
10 40 20
ns
15 30 15
RESET OPERATION
tP L H, tP HL Propagation Delay Time
5 200 400
10 100 200 ns
15 80 160
tW Reset Pulse Width
5 200 100
10 80 40
15 60 30
ns
* If more than unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation delay
at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
5/12
5 Page 
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
HCC/HCF4015B
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
P027A
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HCF4015B.PDF ] | |
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