DataSheet.es T-52017D121J-FW-ABN Hoja de datos PDF



PDF T-52017D121J-FW-ABN Datasheet ( Hoja de datos )

Número de pieza T-52017D121J-FW-ABN
Descripción SVGA Display Module
Fabricantes OPTREX 
Logotipo OPTREX Logotipo
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T-52017D121J-FW-ABN datasheet

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T-52017D121J-FW-ABN pdf
3. ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
MIN.
MAX
UNIT
Power Supply Voltage for LCD
VCC
0
4.0 V
Logic Input Voltage
VI 0.3 VCC0.3 V
Lamp Voltage
VL
0
2000
Vrms
Lamp Current
IL 0 18 mArms
Lamp Frequency
FL -- 80 kHz
Operation Temperature(Panel)
Note 1,2)
Top(Panel)
20
70 °C
Operation Temperature(Ambient) Note 2)
Top(Ambient)
20
70 °C
Storage Temperature
Note 2)
Tstg
20
80 °C
[Note]
1) Measured at the center of active area and at the center of panel back surface
2) Top,Tstg 40C : 90%RH max. without condensation
Top,Tstg > 40C : Absolute humidity shall be less than the value of 90%RH at 40C without
condensation.
4. ELECTRICAL CHARACTERISTICS
(1) TFT-LCD
ITEM
SYMBOL MIN.
Power Supply Voltages for LCD
Power Supply Currents for LCD
Permissive Input Ripple Voltage
VCC
ICC
VRP
3.0
--
--
*1) Power and signals sequence:
t1 10ms
0 < t2 50 ms
0 < t3 50 ms
200 ms t4
200 ms t5
0 t6
TYP.
3.3
300
--
Ambient temperature: Ta = 25
MAX. UNIT
Remarks
3.6 V
*1)
450 mA VCC = 3.3 V *2)
100 mVp-p VCC = 3.3V
LCD Power Supply
0.9 VCC
Logic Signal
0. 1VC C
VCC
data
0.9 V CC
0.1 V CC
0.1 VCC
t1 t2
B ackligh t
t3
t4
Backlight Power Supply
t5 t6
data: RGB DATA, DCL, DENA
OPTREX Confidential
(5/23)
T-52017D121J-FW-ABN

5 Page

T-52017D121J-FW-ABN arduino
6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
DCLK
Frequency
Period
fCLK
tCLK
35
23.8
40 42 MHz
25 28.6
ns
Active Time tHA 800 800 800 tCLK
Blanking Time
Horizontal
Frequency
tHB
fH
20
35.2
256 --
37.9 39.2
tCLK
kHz
DENA
Period
Active Time
tH 25.5 26.4 28.4
tVA 600 600 600
s
tH
Vertical
Blanking Time
Frequency
tVB
fV
3
55
28 --
60 64.2
tH
Hz
Period
tV 15.6 16.7 18.2 ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
OPTREX Confidential
(10/23)
T-52017D121J-FW-ABN

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