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PDF 28F102 Data sheet ( Hoja de datos )

Número de pieza 28F102
Descripción CAT28F102
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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No Preview Available ! 28F102 Hoja de datos, Descripción, Manual

CAT28F102
1 Megabit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 45/55/70/90 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
s 0.5 Seconds Typical Chip-Erase
s 12.0V ± 5% Programming and Erase Voltage
s Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algo-
rithm. The instructions are input via the I/O bus, using a
BLOCK DIAGRAM
s 64K x 16 Word Organization
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
s Electronic Signature
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
I/O0–I/O15
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE COMMAND
REGISTER
CE
OE
A0–A15
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
Y-DECODER
X-DECODER
1
Y-GATING
1,048,576-BIT
MEMORY
ARRAY
28F101-1
Doc. No. 25038-0A 2/98 F-1

1 page




28F102 pdf
CAT28F102
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
JEDEC Standard
28F102-45(7)
Vcc=5V+5%
Symbol Symbol Parameter
Min. Max.
28F102-55(7) 28F102-70 (7) 28F102- 90 (8)
Vcc=5V+5%
Min. Max. Min. Max. Min. Max
Unit
tAVAV
tRC
Read Cycle Time
tELQV
tCE
CE Access Time
tAVQV
tACC
Address Access Time
tGLQV
tOE
OE Access Time
tAXQX
tOH
Output Hold from Address
OE/CE Chan
tGLQX
tOLZ(1)(6)
tELQX
tLZ(1)(6)
tGHQZ
tDF(1)(2)
tEHQZ(1)(2)
-
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
tWHGL
Write Recovery Time Before
Read
45
0
0
0
6
55 70
90 ns
45 55 70
90 ns
45 55 70
90 ns
20 25 28 35 ns
00
0 ns
00
0 ns
00
0 ns
15 15 18
20 ns
15 15 25
30 ns
6 6 6 µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
2.0 V
INPUT PULSE LEVELS
0.45 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example) 1.3V
5108 FHD F03
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Figure 3. High Speed A.C. Testing Input/Output Waveform(3)(4)(5)
23.4V V
0.04.50 V
INPUT PULSE LEVELS
2.0 V
1.5V
0.8 V
REFERENCE POINTS
Figure 4. High Speed A.C. Testing Load Circuit (example)
1.3V
1N914
5108 FHD F04
3.3K
DEVICE
UNDER
TEST
OUT
CL = 1300 pF
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For Load and Reference Points see Figures 3 and 4
(8) For Load and Reference Points see Figures 1 and 2
5 Doc. No. 25038-0A 2/98 F-1

5 Page





28F102 arduino
CAT28F102
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 9. During the first write
cycle, the command XX40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing XXC0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Figure 8. A.C. Timing for Programming Operation
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY
COMMAND
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS tAH
CE (E)
tCS
tCH
tCH
tCS
tCH
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
WE (W)
DATA (I/O)
HIGH-Z
tWP
tDS
DATA IN
= XX 40H
tDH
tDS
tWP
DATA IN
tDH
VCC 5.0V
0V
VPP VPPH
VPPL
tVPEL
tWP
tDS
tDH
DATA IN
= XX C0H
tOE
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
28F102 F07
11 Doc. No. 25038-0A 2/98 F-1

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