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PDF UPD42S17405LLA-A60 Data sheet ( Hoja de datos )

Número de pieza UPD42S17405LLA-A60
Descripción 3.3V OPERATION 16M-BIT DYNAMIC RAM
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD42S17405L, 4217405L
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, EDO
Description
The µPD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S17405L can execute CAS before RAS self refresh.
The µPD42S17405L, 4217405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 4,194,304 words by 4 bits organization
• Single +3.3 V ±0.3 V power supply
• Fast access and cycle time
Part number
µPD42S17405L-A50, 4217405L-A50
µPD42S17405L-A60, 4217405L-A60
µPD42S17405L-A70, 4217405L-A70
Power
consumption
Active (MAX.)
660 mW
360 mW
324 mW
Access time
(MAX.)
50 ns
60 ns
70 ns
µPD42S17405L can execute CAS before RAS self refresh
R/W cycle time
(MIN.)
84 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
20 ns
25 ns
30 ns
Part number
Refresh cycle
µPD42S17405L 2,048 cycles/128 ms
µPD4217405L 2,048 cycles/32 ms
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
Power consumption
at standby (MAX.)
0.54 mW
(CMOS level input)
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10068EJ6V0DS00 (6th edition)
Date Published January 1997 N
Printed in Japan
The mark shows major revised points.
©
1995

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UPD42S17405LLA-A60 pdf
µPD42S17405L, 4217405L
Input/Output Pin Functions
The µPD42S17405L, 4217405L have input pins RAS, CAS, WE, OE, A0 to A10 and input/output pins I/O1 to
I/O4.
Pin name
Input/Output
Function
RAS
(Row address strobe)
CAS
(Column address strobe)
A0 to A10
(Address inputs)
WE
(Write enable)
OE
(Output enable)
I/O1 to I/O4
(Data inputs/outputs)
Input
Input
Input
Input
Input
Input/Output
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Address bus.
Input total 22-bit of address signal, upper 11-bit and lower 11-bit in sequence
(address multiplex method).
Therefore, one word is selected from 4,194,304-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
4-bit data bus.
I/O1 to I/O4 are used to input/output data.
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UPD42S17405LLA-A60 arduino
µPD42S17405L, 4217405L
Notes 1. In CAS before RAS refresh cycles, tRAS (MAX.) is 100 µs.
If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from RAS
tRAD tRAD (MAX.) and tRCD tRCD (MAX.)
tRAD > tRAD (MAX.) and tRCD tRCD (MAX.)
tRAC (MAX.)
tAA (MAX.)
tRAC (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the µPD42S17405L.
Read Cycle
Parameter
Symbol
tRAC = 50 ns
MIN. MAX.
tRAC = 60 ns
MIN. MAX.
tRAC = 70 ns
Unit Notes
MIN. MAX.
Access time from RAS
tRAC – 50 – 60 – 70 ns 1
Access time from CAS
tCAC – 13 – 15 – 18 ns 1
Access time from column address
tAA – 25 – 30 – 35 ns 1
Access time from OE
tOEA – 13 – 15 – 18 ns
Column address lead time referenced to RAS
tRAL 25 – 30 – 35 – ns
Read command setup time
tRCS 0 – 0 – 0 – ns
Read command hold time referenced to RAS
tRRH
0
0
0
– ns 2
Read command hold time referenced to CAS
tRCH
0
0
0
– ns 2
Output buffer turn-off delay time from OE
tOEZ 0 10 0 13 0 15 ns 3
CAS hold time to OE
tCHO
5
5
5
– ns 4
Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAD tRAD (MAX.) and tRCD tRCD (MAX.)
tRAD > tRAD (MAX.) and tRCD tRCD (MAX.)
tRCD > tRCD (MAX.)
Access time
tRAC (MAX.)
tAA (MAX.)
tCAC (MAX.)
Access time from RAS
tRAC (MAX.)
tRAD + tAA (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.
4. WE: inactive (in read cycle)
CAS: inactive, OE: active ····· tCHO is effective.
CAS, OE: active ····· tOCH is effective.
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