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PDF UPD42S65405LE-A50 Data sheet ( Hoja de datos )

Número de pieza UPD42S65405LE-A50
Descripción 64M-BIT DYNAMIC RAM
Fabricantes NEC 
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No Preview Available ! UPD42S65405LE-A50 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4264405, 42S65405, 4265405
64 M-BIT DYNAMIC RAM
16 M-WORD BY 4-BIT, EDO
Description
The µPD4264405, 42S65405, 4265405 are 16,777,216 words by 4 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S65405 can execute CAS before RAS self refresh.
These are packaged in 32-pin plastic TSOP (II) and 32-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 16,777,216 words by 4 bits organization
• Single +3.3 V ± 0.3 V power supply
• Fast access and cycle time
Part number
µPD4264405-A50
µPD42S65405-A50, 4265405-A50
µPD4264405-A60
µPD42S65405-A60, 4265405-A60
Power consumption Access time
Active (MAX.)
(MAX.)
360 mW
468 mW
50 ns
324 mW
396 mW
60 ns
R/W cycle time
(MIN.)
84 ns
104 ns
EDO (Hyper page mode)
cycle time (MIN.)
20 ns
25 ns
• The µPD42S65405 can execute CAS before RAS self refresh.
Part number
µPD42S65405
Refrech cycle
4,096 cycles/128 ms
µPD4264405
µPD4265405
8,192 cycles/64 ms
4,096 cycles/64 ms
4,096 cycles/64 ms
Refresh
RAS only refresh, Normal read/write,
CAS before RAS self refresh,
CAS before RAS refresh, Hidden refresh
RAS only refresh, Normal read/write
CAS before RAS refresh, Hidden refresh
RAS only refresh, Normal read/write,
CAS before RAS refresh, Hidden refresh
Power consumption
at standby (MAX.)
0.72 mW
(CMOS level input)
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10856EJ6V0DS00 (6th edition)
Date Published September 1997 N
Printed in Japan
The mark shows major revised points.
© 1995

1 page




UPD42S65405LE-A50 pdf
µPD4264405, 42S65405, 4265405
Input/Output Pin Functions
The µPD4264405, 42S65405, 4265405 have input pins RAS, CAS, WE, OE, AddressNote and input/output
pins I/O1 to I/O4.
Pin name
Input/Output
Function
RAS
(Row address strobe)
CAS
(Column address strobe)
A0 to A×Note
(Address inputs)
WE
(Write enable)
OE
(Output enable)
I/O1 to I/O4
(Data inputs/outputs)
Input
Input
Input
Input
Input
Input/Output
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS self refresh, CAS before RAS refresh
CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Address bus.
Input total 24-bit of address signal, upper bits and lower bitsNote in sequence
(address multiplex method).
Therefore, one word is selected from 16,777,216-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
4-bit data bus.
I/O1 to I/O4 are used to input/output data.
Note
Part number
µPD4264405
µPD42S65405, 4265405
Address inputs
A0 - A12
A0 - A11
Upper bits
13
12
Lower bits
11
12
5

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UPD42S65405LE-A50 arduino
µPD4264405, 42S65405, 4265405
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
(2) Output timing specification
VIH (MIN.) = 2.0 V
VIL (MAX.) = 0.8 V
tT = 2 ns
(3) Output load condition
tT = 2 ns
VOH (MIN.) = 2.0 V
VOL (MAX.) = 0.8 V
I/O
100 pF
CL
VCC
1,180
870
Common to Read, Write, Read Modify Write Cycle
Parameter
Read / Write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
CAS pulse width
RAS hold time
CAS hold time
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
OE lead time referenced to RAS
CAS to data setup time
OE to data setup time
OE to data delay time
Transition time (rise and fall)
Refresh time
µPD42S65405
µPD4264405, 4265405
Symbol
tRAC = 50 ns
MIN. MAX.
tRAC = 60 ns
Unit Notes
MIN. MAX.
tRC 84 – 104 – ns
tRP 30 – 40 – ns
tCPN 7 – 10 – ns
tRAS 50 10,000 60 10,000 ns 1
tCAS 8 10,000 10 10,000 ns
tRSH 13 – 15 – ns
tCSH 38 – 40 – ns
tRCD 11 37 14 45 ns 2
tRAD 9 25 12 30 ns 2
tCRP 5 – 5 – ns 3
tASR 0 – 0 – ns
tRAH 7 – 10 – ns
tASC 0 – 0 – ns
tCAH 7 – 10 – ns
tOES 0 – 0 – ns
tCLZ 0 – 0 – ns
tOLZ 0 – 0 – ns
tOED
10
13
– ns
tT 1 50 1 50 ns
tREF – 128 – 128 ms 4
– 64 – 64 ms
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