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PDF FQP3N60C Data sheet ( Hoja de datos )

Número de pieza FQP3N60C
Descripción N-Channel MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FQP3N60C Hoja de datos, Descripción, Manual

FQP3N60C
N-Channel QFET® MOSFET
600 V, 3.0 A, 3.4 Ω
Description
This N-Channel enhancement mode power MOSFET is produced
using Fairchild Semiconductor’s proprietary planar stripe and
DMOS technology. This advanced MOSFET technology has
been especially tailored to reduce on-state resistance, and to
provide superior switching performance and high avalanche
energy strength. These devices are suitable for switched mode
power supplies, active power factor correction (PFC), and
electronic lamp ballasts.
December 2013
Features
3.0 A, 600 V, RDS(on) = 3.4 (Max.) @ VGS = 10 V, ID = 1.5 A
• Low Gate Charge (Typ. 10.5 nC)
• Low Crss (Typ. 5.0 pF)
• 100% Avalanche Tested
D
GDS TO-220
G
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
Gate-Source voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering,
1/8” from Case for 5 Seconds
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
FQP3N60C
600
3
1.8
12
±30
150
3
7.5
4.5
75
0.62
-55 to +150
300
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
©2006 Fairchild Semiconductor Corporation
FQP3N60C Rev C1
1
FQP3N60C
1.67
62.5
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Unit
oC/W
www.fairchildsemi.com

1 page




FQP3N60C pdf
Same Type
50KΩ as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
IG = const.
DUT
Charge
Figure 12. Gate Charge Test Circuit & Waveform
VGS
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
Figure 13. Resistive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS = --21-- L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
VGS
DUT
VDD
VDS (t)
t p t p Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2006 Fairchild Semiconductor Corporation
FQP3N60C Rev C1
5
www.fairchildsemi.com

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