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PDF M2S1G64CBH4B5P Data sheet ( Hoja de datos )

Número de pieza M2S1G64CBH4B5P
Descripción Unbuffered DDR3 SO-DIMM
Fabricantes Nanya 
Logotipo Nanya Logotipo



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M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Based on DDR3-1066/1333/1600 128Mx16 (1GB) / 256Mx8 (2GB) / 256Mx8 (4GB) SDRAM B-Die
Features
•Performance:
Speed Sort
PC3-8500 PC3-10600 PC3-12800
-BE -CG
-DI Unit
DIMM CAS Latency
7 9 11
fck Clock Frequency
533 667
800
tck Clock Cycle
1.875
1.5
1.25
fDQ DQ Burst Frequency 1066
1333
1600
204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
1GB: 128Mx64 Unbuffered DDR3 SO-DIMM based on 128Mx16
MHz
ns
Mbps
Programmable Operation:
- DIMM  Latency: 5, 6, 7, 8/PC3-8500; 5, 6, 7, 8,
DDR3 SDRAM B-Die devices.
2GB: 256Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
9/PC3-10600; 5, 6, 7, 8, 9, 10, 11/PC3-12800
- Burst Type: Sequential or Interleave
DDR3 SDRAM B-Die devices.
4GB: 512Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
DDR3 SDRAM B-Die devices.
Intended for 533MHz/667MHz/800MHz applications
• Inputs and outputs are SSTL-15 compatible
VDD = VDDQ = 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
DRAM DLL aligns DQ and DQS transitions with clock transitions.
Address and control signals are fully synchronous to positive
clock edge
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
Two different termination values (Rtt_Nom & Rtt_WR)
14/10/1 (row/column/rank) Addressing for 1GB
15/10/1 (row/column/rank) Addressing for 2GB
15/10/2 (row/column/rank) Addressing for 4GB
Extended operating temperature rage
Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
1GB: SDRAMs are in 96-ball BGA Package
2GB: SDRAMs are in 78-ball BGA Package
4GB: SDRAMs are in 78-ball BGA Package
RoHS compliance and Halogen free
Description
M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N are un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous
DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 128Mx64 (1GB) and one rank of 256Mx64 (2GB)
/ 512Mx64 (4GB) high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices and eight 256Mx8 (2GB)
78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw
cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All Elixir DDR3 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz/800MHz clock speeds and achieves high-speed data transfer
rates of 1066Mbps/1333Mbps/1600Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A13 (1GB)/A0-A14 (2GB/4GB) and I/O inputs BA0~BA2 using the mode register set
cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
09/2010
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

1 page




M2S1G64CBH4B5P pdf
M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Functional Block Diagram
[1GB 1 Rank, 128Mx16 DDR3 SDRAMs]
DQS0

DM0
DQ[0:15]
DQS1

DM1
LDQS
L
LDM
DQ[0:15]
UDQS

UDM
240ohm
+/-1%
ZQ
D0
DQS2

DM2
DQ[16:31]
DQS3

DM3
LDQS
L
LDM
DQ[0:15]
UDQS

UDM
240ohm
+/-1%
ZQ
D1
DQS4

DM4
DQ[32:47]
DQS5

DM5
LDQS
L
LDM
DQ[0:15]
UDQS

UDM
240ohm
+/-1%
ZQ
D2
DQS6

DM6
DQ[48:63]
DQS7

DM7
LDQS
L
LDM
DQ[0:15]
UDQS

UDM
240ohm
+/-1%
ZQ
D3
Vtt
VDD
SCL SCL
SA0 A0 SPD
SA1 A1
A2 WP
SDA
Vtt
VDDSPD
VREFCA
VREFDQ
VDD
VSS
CK0

CK1


Vtt
SPD
D0-D7
D0-D7
D0-D7
D0-D7, SPD
D0-D3
D0-D3
D4-D7
D4-D7
D0-D7
Notes :
1. DQ wiring may differ from that shown however, DQ, DM,
DQS, and relationships are maintained as shown.
Vtt
REV 1.2
09/2010
5
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

5 Page





M2S1G64CBH4B5P arduino
M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Environmental Requirements
Symbol
Parameter
Rating
Units
TOPR
Operating Temperature (ambient)
0 to 85
°C
TSTG
Storage Temperature
-55 to +100
°C
Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Note
VDD Voltage on VDD pins relative to Vss
-0.4 V ~ 1.975 V
V 1, 3
VDDQ
Voltage on VDDQ pins relative to Vss
-0.4 V ~ 1.975 V
V 1, 3
VIN, VOUT Voltage on I/O pins relative to Vss
-0.4 V ~ 1.975 V V 1
TSTG
Storage Temperature
-55 to +100
°C 1, 2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater
Operating temperature Conditions
Symbol
Parameter
Rating
Units
Note
TOPER
Normal Operating Temperature Range
Extended Temperature Range
0 to 85
85 to 95
°C 1, 2
°C 1, 3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions,
please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full
specifications are supported in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify
a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh
mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option
availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
DC Electrical Characteristics and Operating Conditions
Symbol
Parameter
Min Typ
VDD Supply Voltage
1.425
1.5
VDDQ Output Supply Voltage
1.425
1.5
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Max
1.575
1.575
Units
V
V
Notes
1,2
1,2
REV 1.2
09/2010
11
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

11 Page







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