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PDF M471B5273CH0 Data sheet ( Hoja de datos )

Número de pieza M471B5273CH0
Descripción 204pin Unbuffered SODIMM
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! M471B5273CH0 Hoja de datos, Descripción, Manual

Rev. 1.31, Jul. 2012
M471B5773CHS
M471B5273CH0
204pin Unbuffered SODIMM
based on 2Gb C-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
1.35V
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2012 Samsung Electronics Co., Ltd. All rights reserved.
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M471B5273CH0 pdf
Unbuffered SODIMM
datasheet
Rev. 1.31
DDR3L SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin
1 VREFDQ 2
3 VSS 4
5 DQ0 6
VSS
DQ4
DQ5
71 VSS 72 VSS 139 VSS 140
KEY 141 DQ34 142
73 CKE0 74 CKE1 143 DQ35 144
7 DQ1 8 VSS 75 VDD 76 VDD 145 VSS 146
9 VSS 10 DQS0 77 NC 78 A153 147 DQ40 148
11 DM0 12 DQS0 79 BA2 80 A143 149 DQ41 150
13 VSS 14 VSS 81 VDD 82 VDD 151 VSS 152
15 DQ2 16 DQ6 83 A12/BC 84
A11 153 DM5 154
17 DQ3 18 DQ7 85 A9 86 A7 155 VSS 156
19 VSS 20 VSS 87 VDD 88 VDD 157 DQ42 158
21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160
23 DQ9 24 DQ13 91 A5 92 A4 161 VSS 162
25 VSS 26 VSS 93 VDD 94 VDD 163 DQ48 164
27 DQS1 28
DM1
95
A3
96
A2 165 DQ49 166
29 DQS1 30 RESET 97 A1 98 A0 167 VSS 168
31 VSS 32 VSS 99 VDD 100 VDD 169 DQS6 170
33
DQ10
34
DQ14
101
CK0
102
CK1
171 DQS6 172
35
DQ11
36
DQ15
103
CK0
104
CK1
173
VSS
174
37 VSS 38 VSS 105 VDD 106 VDD 175 DQ50 176
39
DQ16
40
DQ20
107 A10/AP 108
BA1
177 DQ51 178
41
DQ17
42
DQ21
109
BA0
110
RAS
179
VSS
180
43 VSS 44 VSS 111 VDD 112 VDD 181 DQ56 182
45 DQS2 46
DM2
113
WE
114
S0
183 DQ57 184
47 DQS2 48
VSS 115 CAS 116 ODT0 185 VSS 186
49
VSS
50
DQ22
117
VDD
118
VDD
187 DM7 188
50
DQ18
52
DQ23
119
A133
120
ODT1
189
VSS
190
53 DQ19 54 VSS 121 S1 122 NC 191 DQ58 192
55
VSS
56
DQ28
123
VDD
124
VDD
193 DQ59 194
57
DQ24
58
DQ29
125
TEST
126 VREFCA 195
VSS
196
59 DQ25 60
VSS 127 VSS 128 VSS 197 SA0 198
61
VSS
62
DQS3
129
DQ32
130
DQ36
199 VDDSPD 200
63 DM3 64 DQS3 131 DQ33 132 DQ37 201 SA1 202
65 VSS 66 VSS 133 VSS 134 VSS 203 VTT 204
67 DQ26 68 DQ30 135 DQS4 136 DM4
69 DQ27 70 DQ31 137 DQS4 138 VSS
NOTE :
1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Back
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7
DQS7
VSS
DQ62
DQ63
VSS
NC
SDA
SCL
VTT
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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M471B5273CH0 arduino
Unbuffered SODIMM
datasheet
Rev. 1.31
DDR3L SDRAM
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 1 ] Single Ended AC and DC input levels for Command and Address
Symbol
Parameter
Min.
DDR3-800/1066/1333/1600
Max.
Unit NOTE
1.35V
VIH.CA(DC90) DC input logic high
VIL.CA(DC90) DC input logic low
VIH.CA(AC160) AC input logic high
VIL.CA(AC160) AC input logic low
VIH.CA(AC135) AC input logic high
VIL.CA(AC135) AC input logic lowM
VREFCA(DC)
Reference Voltage for ADD,
CMD inputs
VREF + 90
VSS
VREF + 160
Note 2
VREF+135
Note 2
0.49*VDD
VDD
VREF - 90
Note 2
VREF - 160
Note 2
VREF-135
0.51*VDD
mV 1,5a)
mV 1,6a)
mV 1,2
mV 1,2
mV 1,2
mV 1,2
V 3,4
1.5V
VIH.CA(DC100) DC input logic high
VIL.CA(DC100) DC input logic low
VIH.CA(AC175) AC input logic high
VIL.CA(AC175) AC input logic low
VIH.CA(AC150) AC input logic high
VIL.CA(AC150) AC input logic low
VREFCA(DC)
Reference Voltage for ADD,
CMD inputs
VREF + 100
VSS
VREF + 175
Note 2
VREF+150
Note 2
0.49*VDD
VDD
VREF - 100
Note 2
VREF - 175
Note 2
VREF-150
0.51*VDD
mV 1,5b)
mV 1,6b)
mV 1,2,7
mV 1,2,8
mV 1,2,7
mV 1,2,8
V 3,4
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.CA(a) 1.35V : DC90, b) 1.5V : DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(a) 1.35V : DC90, b) 1.5V : DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is
used when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used
when VREF - 150mV is referenced.
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