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PDF M2Y1G64TU88G7B Data sheet ( Hoja de datos )

Número de pieza M2Y1G64TU88G7B
Descripción Unbuffered DDR2 SDRAM DIMM
Fabricantes Nanya 
Logotipo Nanya Logotipo



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M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
240pin Unbuffered DDR2 SDRAM MODULE
Based on 128Mx8 DDR2 SDRAM G-die
Features
Performance:
PC2-5300 PC2-6400 PC2-8500
Speed Sort
-3C -AC -BD Unit
DIMM  Latency*
5
5
6
f CK Clock Frequency 333 400 533 MHz
t CK Clock Cycle
3
2.5
1.875
ns
f DQ DQ Burst Frequency
667
800
1066
Mbps
Programmable Operation:
JEDEC Standard 240-pin Dual In-Line Memory Module
- Device  Latency: 3, 4, 5, 6
128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on
- Burst Length: 4, 8
Elixir 128Mx8 DDR2 SDRAM G-die component
• Auto Refresh (CBR) and Self Refresh Modes
Double Data Rate architecture; two data transfer per clock cycle
• Automatic and controlled precharge commands
Differential bi-directional data strobe (DQS & )
14/10/1 Addressing (row/column/rank) 1GB
DQS is edge-aligned with data for reads and is center-aligned
14/10/2 Addressing (row/column/rank) 2GB
with data for writes
• Serial Presence Detect
Differential clock inputs (CK & )
• On Die Termination (ODT)
Intended for 333MHz/400MHz applications
OCD impedance adjustment.
• Inputs and outputs are SSTL-18 compatible
• Gold contacts
VDD = VDDQ = 1.8V ± 0.1V
• 7.8 μs Max. Average Periodic Refresh Interval
SDRAMs in 60-ball BGA Package
• RoHs Compliance.
Description
M2Y1G64TU88G7B and M2Y2G64TU8HG5B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as one rank 128Mx64 and two ranks 256Mx64 high-speed memory array. M2Y1G64TU88G7B
uses eight 128Mx8 DDR2 SDRAMs and M2Y2G64TU8G5B uses sixteen 128Mx8 DDR2 SDRAMs in BGA packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz (or 400MHz/533MHz) clock speeds and achieves high-speed data
transfer rates of up to 667Mbps (or 800Mbps/1066Mbps). Prior to any access operation, the device  latency and burst / length
/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1 and BA2 using the mode register
set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 0.1
01/2010
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1 page




M2Y1G64TU88G7B pdf
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
Functional Block Diagram (1GB, 1 Rank, 128Mx8 DDR2 SDRAMs)
CS 0
DQS 0
DQS0
DM 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQS 1
DQS 1
DM1
DQ 8
DQ 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D0
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D1
I/O 4
I/O 5
I/O 6
I/O 7
DQS 2
DQS 2
DM 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS 3
DQS 3
DM 3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D2
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS 4
DM 4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS 5
DM5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQS6
DQS6
DM 6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS 7
DQS 7
DM 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D4
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D5
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D6
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D7
I/O 4
I/O 5
I/O 6
I/O 7
BA0- BA2
A0 - A13
RAS
CAS
WE
CKE0
ODT0
BA0- BA2: SDRAMs D 0-D7
A0 - A13: SDRAMs D 0-D7
RAS : SDRAMs D 0-D7
CAS : SDRAMs D 0-D7
WE : SDRAMs D 0-D7
CKE : SDRAMs D 0-D7
ODT : SDRAMs D 0-D7
SCL
Serial PD
WP A0
SA0
A1 A 2
SA1 SA2
SDA
VDDSPD
VDD /VDDQ
V REF
VSS
SPD
D0 - D7
D0 - D7
D0 - D7
REV 0.1
01/2010
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

5 Page





M2Y1G64TU88G7B arduino
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
PC2-5300
Min. Max.
PC2-6400
Min. Max.
PC2-8500
Min Max
Txard Exit active power down to read command
2-2-
3
-
Txards Exit active power down to read command
7-AL
8-AL
10 - AL
-
Taond ODT turn-on delay
2222
2
2
Taon ODT turn-on
Tac (min)
Tac
(max)+0.7
Tac (min)
Tac
(max)+0.7
tAC min
tAC max +
2.575
Taonpd ODT turn-on (Power down mode)
Tac (min)
+2
2Tck +
Tac(max)
+1
Tac (min)
+2
2Tck +
Tac(max)
+1
tAC min + 2
3tCK + tAC
max + 1
Taofd ODT turn-off delay
2.5 2.5 2.5 2.5
2.5
2.5
Taof ODT turn-off
Tac(min)
Tac(max)
+0.6
Tac(min)
Tac(max)
+0.6
tAC min
tAC max +
0.6
Taofpd ODT turn-off (Power down mode)
Tac (min)+2
2.5Tck +
Tac(max)
+1
Tac (min)+2
2.5Tck +
Tac(max)
+1
tAC min + 2
2.5tCK+tAC
max + 1
Tanpd ODT to power down entry latency
3-3-
4
-
Taxpd ODT power down exit latency
88
11 -
Tmrd Mode register set command cycle time
2-2-
2
-
Tmod MRS command to ODT update delay
0 12 0 12
0
12
Toit OCD drive mode output delay
0 12 0 12
0
12
tDelay
Minimum time clocks remains ON after CKE Tis + Tck +
asynchronously drops Low
Tih
-
Tis + Tck +
Tih
-
tIS + tCK + tIH
-
Trfc Refresh to active/Refresh command time
127.5
127.5
105
Average Periodic Refresh Interval
(85ºC < TCASE ≤ 95ºC)
Trefi
Average Periodic Refresh Interval
(0ºC ≤ TCASE ≤ 85ºC)
3.9 3.9
7.8 7.8
3.9
7.8
Unit
Nck
Nck
Nck
ns
ns
Nck
ns
ns
Nck
Nck
Nck
ns
ns
ns
ns
μs
μs
Speed Grade Definition
Symbol
Parameter
Tras Row Active Time
Trc Row Cycle Time
Trcd RAS to CAS delay
Trp Row Precharge Time
PC2-5300
Min Max
45 70,000
60 -
15 -
15 -
PC2-6400
Min Max
45 70,000
57.5 -
12.5 -
12.5 -
PC2-8500
Min Max
45 70000
56.25
11.25
11.25
-
-
-
Unit
ns
ns
ns
ns
REV 0.1
01/2010
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

11 Page







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