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PDF M393B5273CH0 Data sheet ( Hoja de datos )

Número de pieza M393B5273CH0
Descripción 240pin Registered DIMM based on 2Gb C-die
Fabricantes Samsung 
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No Preview Available ! M393B5273CH0 Hoja de datos, Descripción, Manual

Rev. 1.01, Dec. 2010
M393B5773CH0
M393B5273CH0
M393B5270CH0
M393B1K70CH0
M393B1K73CH0
M393B2K70CM0
240pin Registered DIMM
based on 2Gb C-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
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1 page




M393B5273CH0 pdf
Registered DIMM
datasheet
Rev. 1.01
DDR3 SDRAM
1. DDR3 Registered DIMM Ordering Information
Part Number2
Density
Organization
Component Composition
M393B5773CH0-CF8/H9/K0
M393B5273CH0-CF8/H9/K0
M393B5270CH0-CF8/H9/K0
M393B1K70CH0-CF8/H9/K0
M393B1K73CH0-CF8/H9
M393B2K70CM0-CF8/H9
2GB
4GB
4GB
8GB
8GB
16GB
256Mx72
512Mx72
512Mx72
1Gx72
1Gx72
2Gx72
256Mx8(K4B2G0846C-HC##)*9
256Mx8(K4B2G0846C-HC##)*18
512Mx4(K4B2G0446C-HC##)*18
512Mx4(K4B2G0446C-HC##)*36
256Mx8(K4B2G0846C-HC##)*36
DDP 1Gx4(K4B4G0446C-MC##)*36
NOTE :
1. "##" - F8/H9/K0
2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11)
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
Number of
Rank
1
2
1
2
4
4
Height
30mm
30mm
30mm
30mm
30mm
30mm
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE 95°C
• Asynchronous Reset
3. Address Configuration
Organization
512Mx4(2Gb) based Module
256Mx8(2Gb) based Module
1Gx4(4Gb DDP) based Module
Row Address
A0-A14
A0-A14
A0-A14
Column Address
A0-A9, A11
A0-A9
A0-A9, A11
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
A10/AP
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5 Page





M393B5273CH0 arduino
Registered DIMM
datasheet
10. Function Block Diagram:
10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
Rev. 1.01
DDR3 SDRAM
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D8
ZQ
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D4
ZQ
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D3
ZQ
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D2
ZQ
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D1
ZQ
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D0
ZQ
Vtt
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D5
ZQ
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D6
ZQ
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D7
ZQ
Vtt
SCL
EVENT
Thermal sensor with SPD
EVENT
A0 A1 A2
SA0 SA1 SA2
SDA
VDDSPD
VDD
VTT
VREFCA
VREFDQ
VSS
Serial PD
D0 - D8
D0 - D8
D0 - D8
D0 - D8
NOTE :
1. ZQ resistors are 240 ± 1% For all other resistor values refer to the appropriate wir-
ing diagram.
S0*
S1*
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RESET**
1:2
R
E
G
I
S
T
E
R
QERR
RST
RS0A-> CS0 : SDRAMs D[3:0], D8
RS0B-> CS0 : SDRAMs D[7:4]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8
RA[N:0]B -> A[N:0] : SDRAMs D[7:4]
RRASA -> RAS : SDRAMs D[3:0], D8
RRASB -> RAS : SDRAMs D[7:4]
RCASA -> CAS : SDRAMs D[3:0], D8
RCASB -> CAS : SDRAMs D[7:4]
RWEA -> WE : SDRAMs D[3:0], D8
RWEB -> WE : SDRAMs D[7:4]
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
RCKE0B -> CKE0 : SDRAMs D[7:4]
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0A -> CK : SDRAMs D[7:4]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0A -> CK : SDRAMs D[7:4]
Err_out
RST** : SDRAMs D[8:0]
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)
- 11 -

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