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PDF M393B4G70BM0 Data sheet ( Hoja de datos )

Número de pieza M393B4G70BM0
Descripción 240pin Registered DIMM based on 4Gb B-die
Fabricantes Samsung 
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No Preview Available ! M393B4G70BM0 Hoja de datos, Descripción, Manual

Rev. 1.5, Aug. 2012
M393B1G70BH0
M393B1G73BH0
M393B2G70BH0
M393B2G73BH0
M393B4G70BM0
240pin Registered DIMM
based on 4Gb B-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2012 Samsung Electronics Co., Ltd. All rights reserved.
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1 page




M393B4G70BM0 pdf
Registered DIMM
datasheet
Rev. 1.5
DDR3 SDRAM
1. DDR3 Registered DIMM Ordering Information
Part Number2
Density
Organization
Component Composition1
M393B1G70BH0-CF8/H9/K0/MA
M393B1G73BH0-CF8/H9/K0/MA
M393B2G70BH0-CF8/H9/K0/MA
M393B2G73BH0-CF8/H9
M393B4G70BM0-CF8/H9
8GB
8GB
16GB
16GB
32GB
1Gx72
1Gx72
2Gx72
2Gx72
4Gx72
1Gx4(K4B4G0446B-HC##)*18
512Mx8(K4B4G0846B-HC##)*18
1Gx4(K4B4G0446B-HC##)*36
512Mx8(K4B4G0846B-HC##)*36
DDP 2Gx4(K4B8G0446B-MC##)*36
NOTE :
1. "##" - F8/H9/K0/MA
2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)
- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
Number of
Rank
1
2
2
4
4
Height
30mm
30mm
30mm
30mm
30mm
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
DDR3-1866
13-13-13
1.071
13
13.91
13.91
34
47.91
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
933MHz fCK for 1866Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11,13
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333), 8(DDR3-1600) and 9(DDR3-1866)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85C, 3.9us at 85C < TCASE 95C
• Asynchronous Reset
3. Address Configuration
Organization
1Gx4(4Gb) based Module
512Mx8(4Gb) based Module
2Gx4(8Gb DDP) based Module
Row Address
A0-A15
A0-A15
A0-A15
Column Address
A0-A9, A11
A0-A9
A0-A9, A11
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
A10/AP
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5 Page





M393B4G70BM0 arduino
Registered DIMM
datasheet
10. Function Block Diagram:
10.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)
Rev. 1.5
DDR3 SDRAM
DQS8
DQS8
VSS
CB[3:0]
DQS
DQS
DM
DQ[3:0]
D8
ZQ
DQS17
DQS17
VSS
CB[7:4]
DQS
ZQ DQS4
DQS
DQS4
DM
DQ[3:0]
D17
VSS
DQ[35:32]
DQS
ZQ DQS13
DQS
DQS13
DM
DQ[3:0]
D4
VSS
DQ[39:36]
DQS
DQS
DM
DQ[3:0]
D13
ZQ
DQS3
DQS3
VSS
DQ[27:24]
DQS
ZQ DQS12
DQS
DQS12
DM
DQ[3:0]
D3
VSS
DQ[31:28]
DQS
ZQ DQS5
DQS
DQS5
DM
DQ[3:0]
D12
VSS
DQ[43:40]
DQS
ZQ DQS14
DQS
DQS14
DM
DQ[3:0]
D5
VSS
DQ[47:44]
DQS
DQS
DM
DQ[3:0]
D14
ZQ
DQS8
DQS2
VSS
DQ[19:16]
DQS
ZQ DQS11
DQS
DQS11
DM
DQ[3:0]
D2
VSS
DQ[23:20]
DQS
ZQ DQS6
DQS
DQS6
DM
DQ[3:0]
D11
VSS
DQ[51:48]
DQS
ZQ DQS15
DQS
DQS15
DM
DQ[3:0]
D6
VSS
DQ[55:52]
DQS
DQS
DM
DQ[3:0]
D15
ZQ
DQS1
DQS1
VSS
DQ[11:8]
DQS
ZQ DQS10
DQS
DQS10
DM
DQ[3:0]
D1
VSS
DQ[15:12]
DQS
ZQ DQS7
DQS
DQS7
DM
DQ[3:0]
D10
VSS
DQ[59:56]
DQS
ZQ DQS16
DQS
DQS16
DM
DQ[3:0]
D7
VSS
DQ[63:60]
DQS
DQS
DM
DQ[3:0]
D16
ZQ
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
D0
ZQ
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
DQ[3:0]
D9
ZQ
Vtt
SCL
EVENT
Thermal sensor with SPD
EVENT
A0 A1 A2
SA0 SA1 SA2
VDDSPD
SDA VDD
VTT
VREFCA
VREFDQ
VSS
Serial PD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
NOTE :
1. Unless otherwise noted, resistor values are 15 5%.
2. See the wiring diagrams for all resistors associated with the command, address
and control bus.
3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate
wiring diagram.
Vtt
S0*
S1*
S[3:2] NC
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
1:2
R
E
G
I
S
T
E
R
120
CK1
CK1
PAR_IN
RESET**
120
RST
RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B-> CS0 : SDRAMs D[7:4], D[16:13]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]
RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17
RRASB -> RAS : SDRAMs D[7:4], D[16:13]
RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
RCASB -> CAS : SDRAMs D[7:4], D[16:13]
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17
RWEB -> WE : SDRAMs D[7:4], D[16:13]
RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]
RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK : SDRAMs D[7:4], D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK : SDRAMs D[7:4], D[16:13]
Err_out
RST** : SDRAMs D[17:0]
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