PDF M474B1G73QH0 Data sheet ( Hoja de datos )

Número de pieza	M474B1G73QH0
Descripción	204pin Unbuffered SODIMM based on 4Gb Q-die
Fabricantes	Samsung
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No Preview Available ! Rev. 1.21, Oct. 2013 M471B5674QH0 M471B5173QH0 M471B1G73QH0 M474B5173QH0 M474B1G73QH0 204pin Unbuffered SODIMM based on 4Gb Q-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.35V datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. (C) 2013 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page Unbuffered SODIMM datasheet Rev. 1.21 DDR3L SDRAM 4. x64 DIMM Pin Configurations (Front side/Back Side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin 1 VREFDQ 2 3 VSS 4 5 DQ0 6 VSS DQ4 DQ5 71 VSS 72 VSS 139 VSS 140 KEY 141 DQ34 142 73 CKE0 74 CKE1 143 DQ35 144 7 DQ1 8 VSS 75 VDD 76 VDD 145 VSS 146 9 VSS 10 DQS0 77 NC 78 A153 147 DQ40 148 11 DM0 12 DQS0 79 BA2 80 A143 149 DQ41 150 13 VSS 14 VSS 81 VDD 82 VDD 151 VSS 152 15 DQ2 16 DQ6 83 A12/BC 84 A11 153 DM5 154 17 DQ3 18 DQ7 85 A9 86 A7 155 VSS 156 19 VSS 20 VSS 87 VDD 88 VDD 157 DQ42 158 21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 23 DQ9 24 DQ13 91 A5 92 A4 161 VSS 162 25 VSS 26 VSS 93 VDD 94 VDD 163 DQ48 164 27 DQS1 28 DM1 95 A3 96 A2 165 DQ49 166 29 DQS1 30 RESET 97 A1 98 A0 167 VSS 168 31 VSS 32 VSS 99 VDD 100 VDD 169 DQS6 170 33 DQ10 34 DQ14 101 CK0 102 CK1 171 DQS6 172 35 DQ11 36 DQ15 103 CK0 104 CK1 173 VSS 174 37 VSS 38 VSS 105 VDD 106 VDD 175 DQ50 176 39 DQ16 40 DQ20 107 A10/AP 108 BA1 177 DQ51 178 41 DQ17 42 DQ21 109 BA0 110 RAS 179 VSS 180 43 VSS 44 VSS 111 VDD 112 VDD 181 DQ56 182 45 DQS2 46 DM2 113 WE 114 S0 183 DQ57 184 47 DQS2 48 VSS 115 CAS 116 ODT0 185 VSS 186 49 VSS 50 DQ22 117 VDD 118 VDD 187 DM7 188 51 DQ18 52 DQ23 119 A133 120 ODT1 189 VSS 190 53 DQ19 54 VSS 121 S1 122 NC 191 DQ58 192 55 VSS 56 DQ28 123 VDD 124 VDD 193 DQ59 194 57 DQ24 58 DQ29 125 TEST 126 VREFCA 195 VSS 196 59 DQ25 60 VSS 127 VSS 128 VSS 197 SA0 198 61 VSS 62 DQS3 129 DQ32 130 DQ36 199 VDDSPD 200 63 DM3 64 DQS3 131 DQ33 132 DQ37 201 SA1 202 65 VSS 66 VSS 133 VSS 134 VSS 203 VTT 204 67 DQ26 68 DQ30 135 DQS4 136 DM4 69 DQ27 70 DQ31 137 DQS4 138 VSS NOTE : 1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. Back DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS NC SDA SCL VTT SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. -5- 5 Page Unbuffered SODIMM datasheet 9.2 4GB, 512Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) Rev. 1.21 DDR3L SDRAM DQS0 DQS0 DM0 DQ[0:7] DQS DQS 2401% DM ZQ DQ[0:7] D0 DQS1 DQS1 DM1 DQ[8:15] DQS DQS 2401% DM ZQ DQ[0:7] D4 SCL SA0 SA1 SCL A0 A1 A2 (SPD) WP SDA DQS2 DQS2 DM2 DQ[16:23] DQS DQS 2401% DM ZQ DQ[0:7] D1 DQS3 DQS3 DM3 DQ[24:31] DQS DQS 2401% DM ZQ DQ[0:7] D5 DQS4 DQS4 DM4 DQ[32:39] DQS DQS DM 2401% ZQ DQ[0:7] D2 DQS5 DQS5 DM5 DQ[40:47] DQS DQS DM 2401% ZQ DQ[0:7] D6 Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK0 CK1 CK1 S1 ODT1 CKE1 RESET Vtt SPD D0 - D7 D0 - D7 D0 - D7 D0 - D7, SPD D0 - D7 D0 - D7 Terminated near card edge NC NC NC D0 - D7 V1 D4 V2 D5 V3 D6 V4 D7 DQS6 DQS6 DM6 DQ[48:55] DQS DQS 2401% DM ZQ DQ[0:7] D3 DQS7 DQS7 DM7 DQ[56:63] DQS DQS 2401% DM ZQ DQ[0:7] D7 Vtt Vtt VDD V1 D0 V2 D1 V3 D2 V4 D3 Address and Controllines NOTE : 1. DQ wiring may differ from that shown how- ever ,DQ, DM, DQS and DQS relationships are maintained as shown Rank0 - 11 - 11 Page

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