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PDF LAN9221i Data sheet ( Hoja de datos )
| Número de pieza | LAN9221i | |
| Descripción | High-Performance 16-bit Non-PCI 10/100 Ethernet Controller | |
| Fabricantes | SMSC | |
| Logotipo |  |
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LAN9221/LAN9221i
High-Performance 16-bit Non-PCI
10/100 Ethernet Controller with
Variable Voltage I/O
PRODUCT FEATURES
Highlights
Optimized for high performance applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
1.8V to 3.3V variable voltage I/O accommodates wide
range of I/O signalling without voltage level shifters
Integrated PHY with HP Auto-MDIX support
Integrated checksum offload engine helps reduce
CPU load
Low pin count and small body size package for small
form factor system designs
Target Applications
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
Digital TV
Digital media clients/servers and home gateways
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
High-end audio distribution systems
Key Benefits
Non-PCI Ethernet controller for high performance
applications
— 16-bit interface with fast bus cycle times
— Burst-mode read support
Minimizes dropped packets
— Internal buffer memory can store over 200 packets
— Automatic PAUSE and back-pressure flow control
Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
Reduced Power Modes
— Numerous power management modes
— Wake on LAN
— Magic packet wakeup
— Wakeup indicator event signal
— Link Status Change
Datasheet
Single chip Ethernet controller
— Fully compliant with IEEE 802.3/802.3u standards
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and Half-duplex support
— Full-duplex flow control
— Backpressure for half-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
Flexible address filtering modes
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast
— Promiscuous mode
— Inverse filtering
— Pass all incoming with status report
— Disable reception of broadcast packets
Integrated 10/100 Ethernet PHY
— Supports HP Auto-MDIX
— Auto-negotiation
— Supports energy-detect power down
Host bus interface
— Simple, SRAM-like interface
— 16-bit data bus
— 16Kbyte FIFO with flexible TX/RX allocation
— One configurable host interrupt
Miscellaneous features
— Small form factor, 56-pin QFN lead-free RoHS
Compliant package
— Integrated 1.8V regulator
— Integrated checksum offload engine
— Mixed endian support
— General Purpose Timer
— Optional EEPROM interface
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
Single 3.3V Power Supply with Variable Voltage I/O
Commercial and Industrial Temperature Support
SMSC LAN9221/LAN9221i
DATASHEET
Revision 2.6 (12-04-08)
1 page  
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
5.3.3 INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.4 INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.5 BYTE_TEST—Byte Order Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.7 RX_CFG—Receive Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.8 TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.9 HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 96
5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 97
5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 98
5.3.17 WORD_SWAP—Word Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . 100
5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . 100
5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . 101
5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4 MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4.1 MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4.2 ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.4.3 ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.4.4 HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.5 HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.6 MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.4.7 MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.4.8 FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.4.9 VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4.13 COE_CR—Checksum Offload Engine Control Register . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.5.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.5.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.3 PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5.5 Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.5.7 Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 129
SMSC LAN9221/LAN9221i
5
DATASHEET
Revision 2.6 (12-04-08)
5 Page 
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
1.1 Block Diagram
System Memory
System
Peripherals
Microprocessor/
Microcontroller
System Bus
LAN9221/
LAN9221i
Magnetics
LEDS/
GPIO
Ethernet
25MHz
XTAL
EEPROM
(Optional)
Figure 1.1 System Block Diagram
The SMSC LAN9221/LAN9221i integrated 10/100 MAC/PHY controller is a peripheral chip that
performs the function of translating parallel data from a host controller into Ethernet packets. The
LAN9221/LAN9221i Ethernet MAC/PHY controller is designed and optimized to function in an
embedded environment. All communication is performed with programmed I/O transactions using the
simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9221/LAN9221i in a
typical embedded environment.
The LAN9221/LAN9221i is a general purpose, platform independent, Ethernet controller. The
LAN9221/LAN9221i consists of four major functional blocks. The four blocks are:
10/100 Ethernet PHY
10/100 Ethernet MAC
RX/TX FIFOs
Host Bus Interface (HBI)
SMSC LAN9221/LAN9221i
11
DATASHEET
Revision 2.6 (12-04-08)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9221i.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LAN9221 | High-Performance 16-bit Non-PCI 10/100 Ethernet Controller | SMSC |
| LAN9221i | High-Performance 16-bit Non-PCI 10/100 Ethernet Controller | SMSC |
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