PDF FM28V102A Data sheet ( Hoja de datos )

Número de pieza	FM28V102A
Descripción	1-Mbit (64 K x 16) F-RAM Memory
Fabricantes	Cypress Semiconductor
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FM28V102A 1-Mbit (64 K × 16) F-RAM Memory 2-Mbit (128 K × 16) F-RAM Memory Features ■ 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 64 K × 16 ❐ Configurable as 128 K × 8 using UB and LB ❐ High-endurance 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 30-ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 64 K × 16 SRAM pinout ❐ 60-ns access time, 90-ns cycle time ■ Advanced features ❐ Software-programmable block write-protect ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 7 mA (typ) ❐ Standby current 120 A (typ) ❐ Sleep mode current 3 A (typ) Logic Block Diagram ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 44-pin thin small outline package (TSOP) Type II ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM28V102A is a 64 K × 16 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM28V102A operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read cycles may be triggered by CE or simply by changing the address and write cycles may be triggered by CE or WE. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V102A ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 400-mil 44-pin TSOP-II surface mount package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. A15-0 CE UB, LB WE OE ZZ A15-2 A 1-0 Control Logic 64 K x 16 F-RAM Array ... Column Decoder I/O Latch & Bus Driver DQ15-0 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-91080 Rev. B • San Jose, CA 95134-1709 • 408-943-2600 Revised June 30, 2014 1 page FM28V102A Figure 2. Sleep/Standby State Diagram Power Applied CE HIGH, ZZ HIGH Standby ZZ LOW Initialize CE LOW, ZZ HIGH CE HIGH, ZZ HIGH CE LOW, ZZ HIGH Normal Operation ZZ LOW Sleep ZZ HIGH SRAM Drop-In Replacement The FM28V102A is designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require CE to toggle for each new address. CE may remain LOW indefinitely. While CE is LOW, the device automatically detects address changes and a new access begins. This functionality allows CE to be grounded, similar to an SRAM. It also allows page mode operation at speeds up to 33 MHz. Figure 3 shows a pull-up resistor on CE, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition. The pull-up resistor value should be chosen to ensure the CE pin tracks VDD to a high enough value, so that the current drawn when CE is LOW is not an issue. A 10-k resistor draws 330 µA when CE is LOW and VDD = 3.3 V Figure 3. Use of Pull-up Resistor on CE VDD MCU / MPU FM28V102A CE WE OE A15-0 DQ 15-0 Note that if CE is tied to ground, the user must be sure WE is not LOW at power-up or power-down events. If CE and WE are both LOW during power cycles, data will be corrupted. Figure 4 shows a pull-up resistor on WE, which will keep the pin HIGH during power cycles, assuming the MCU/MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the WE pin tracks VDD to a high enough value, so that the current drawn when WE is LOW is not an issue. A 10-k resistor draws 330 µA when WE is LOW and VDD = 3.3 V. Figure 4. Use of Pull-up Resistor on WE VDD FM28V102A CE MCU / MPU WE OE A 15-0 DQ15-0 For applications that require the lowest power consumption, the CE signal should be active (LOW) only during memory accesses. The FM28V102A draws supply current while CE is LOW, even if addresses and control signals are static. While CE is HIGH, the device draws no more than the maximum standby current, ISB. The UB and LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 128 K × 8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A16 may be available from the system processor. Figure 5. FM28V102A Wired as 128 K x 8 A16 A15-0 CE ZZ WE 1-Mbit F-RAM OE FM28V102A UB LB A15-0 DQ15-8 DQ7-0 D 7-0 Document Number: 001-91080 Rev. B Page 5 of 20 5 Page FM28V102A A15-2 DQ15-0 Figure 6. Read Cycle Timing 1 (CE LOW, OE LOW) tRC tRC tAA tOH Previous Data tAA tOH Valid Data CE A15-0 tAS Figure 7. Read Cycle Timing 2 (CE Controlled) tCA tAH tPC OE DQ15-0 UB / LB CE A15-2 tAS tOE tCE tBA tHZ tOHZ tOH tBHZ Figure 8. Page Mode Read Cycle Timing [7] tCA tPC A1-0 OE DQ15-0 Col 0 tOE tCE Col 1 Col 2 tAAP tOHP Data 0 Data 1 tHZ tOHZ Data 2 Note 7. Although sequential column addressing is shown, it is not required Valid Data Document Number: 001-91080 Rev. *B Page 11 of 20 11 Page

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