|
|
Número de pieza | QD14WL01 | |
Descripción | TFT LCD Module | |
Fabricantes | Quanta | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de QD14WL01 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
No Preview Available ! Final Spec.
QD14WL0102 Page 1 /25
Doc No. QD14WL0102
Doc. REV.: 01
Quanta Display Inc.
SPECIFICATION
Issue Date: 12/10/2004
With RoHS
Compliant
Specification for TFT LCD Module
Model No.
QD14WL01 Rev.:02
Approved By
. Quanta Display Inc.
1 page 4. Input Connectors
QD14WL0102 Page 5 /25
4-1 Signal Interface Connector
CN1 (1 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30SL-HF10 (JAE) or equivalent
Interface Cable Pin Assignments
PIN NO
SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6 Clk EEDID DDC Clock
7 DATA EEDID DDC Data
8 Rin0-
- LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+ + LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11 Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+
+ LVDS differential clock input (odd pixels)
19 VSS
Ground
20 NC
No connect
21 NC
No connect
22 VSS
Ground
23 NC
No connect
24 NC
No connect
25 VSS
Ground
26 NC
No connect
27 NC
No connect
28 VSS
Ground
29 NC
No connect
30 NC
No connect
[Note 1] Relation between LVDS signals and actual data shows below section (4-2).
[Note 2] The shielding case is connected with signal GND.
5 Page 7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
Data
ENAB
Sync
QD14WL0102 Page 11/25
Vertical
Item symbol
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back
porch (TVC+TVD)
Active display area (TVE)
Front porch (TVF)
Min.
15.16
784
16
3
3
--
768
3
Typ.
16.67
790
22
7
13
20
768
2
Max.
17.5
840
72
12
43
--
768
43
Unit
ms
line
line
line
line
line
Remark
Negative
line
line
( Horizontal )
Item symbol
Min.
Typ.
Max.
Unit Remark
Hsync cycle (THA)
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
19.2
1380
100
20
12
--
1280
12
21.09
1440
160
32
80
112
1280
48
22.15
1540
260
36
160
--
1280
160
s Negative
Clock
Item
Min.
Typ.
Max.
Unit Remark
Frequency
65 68.25 75 MHz [Note1]
[Note] In case of lower frequency, the deterioration of display quality, flicker etc., may be
occurred.
11 Page |
Páginas | Total 25 Páginas | |
PDF Descargar | [ Datasheet QD14WL01.PDF ] |
Número de pieza | Descripción | Fabricantes |
QD14WL01 | TFT LCD Module | Quanta |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |