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PDF B141EW02-V1 Data sheet ( Hoja de datos )
| Número de pieza | B141EW02-V1 | |
| Descripción | LCD Module | |
| Fabricantes | AUO | |
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www.DataSheet4U.net
Version: 0
Date: 2005/12/06
Product Functional Specification
14.1 inch WXGA Color TFT LCD Module
Model Name: B141EW02 V.1
(u) Preliminary Specification
( ) Final Specification
Note: This Specification is subject to change without notice.
(C) Copyright AU Optronics
Dec., 2003 All Rights Reserved.
No Reproduction and Redistribution Allowed.
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2.0 General Description
This specification applies to the 14.1 inch Color TFT/LCD Module B141EW01
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the WXGA (1280(H) x 800(V)) screen and 262k colors (RGB 6-bits
data driver).
All input signals are LVDS interface compatible.
This module does not contain an inverter card for backlight.
2.1 Display Characteristics
The following items are characteristics summary on the table under 25 ℃ condition:
ITEMS
Unit SPECIFICATIONS
Screen Diagonal
[mm]
357.7 (14.1")
Active Area
[mm]
303.36(H) x 189.6(V)
Pixels H x V
1280(x3) x 800
Pixel Pitch
[mm]
0.237
Pixel Arrangement
R.G.B. Vertical Stripe
Display Mode
Typical White Luminance (CCFL=6.0mA)
[cd/m2]
Normally White
200 Typ., 170 Min. (5 points average)
Contrast Ratio
300:1 Min., 400:1 Typ.
Response Time
[msec] 25 Typ., 35 Max.
Nominal Input Voltage VDD
[Volt]
+3.3 Typ.
Typical Power Consumption
(VDD line + VCFL line)
[Watt]
5.0 Typ.
Weight
[Grams] 400 g Typ., 420 g Max.
Physical Size
[mm]
320 Max(W) x 206 Max.(H) x 5.5(D) Max.
Electrical Interface
R/G/B Data, 3 Sync, Signals, Clock (4 pairs
LVDS)
Support Color
Native 262K colors (RGB 6-bit data driver)
Surface treatment
Haze 25%, Hard coating 3H, Anti-glare type
Temperature Range
Operating
Storage (Shipping)
[oC] 0 to +50
[oC] -20 to +60
RoHS compliance
RoHS compliance
(C) Copyright AU Optronics
Dec., 2003 All Rights Reserved.
No Reproduction and Redistribution Allowed.
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5.3 Signal Description
The module uses a LVDS receiver embedded in AUO’s ASIC. LVDS is a differential signal technology for LCD
interface and high-speed data transfer device.
Signal Name
VEDID
CLKEDID
DATAEDID
RxIN0-, RxIN0+
RxIN1-, RxIN1+
RxIN2-, RxIN2+
RxCLKIN-, RxCLKIN0+
VDD
GND
Description
+3.3V EDID Power
EDID Clock Input
EDID Data Input
LVDS differential data input(Red0-Red5, Green0)
LVDS differential data input(Green1-Green5, Blue0-Blue1)
LVDS differential data input(Blue2-Blue5, Hsync, Vsync, DSPTMG)
LVDS differential clock input
+3.3V Power Supply (Internal 2.5V logic operation)
Ground
Note: Input signals shall be in low status when VDD is off.
Internal circuit of LVDS inputs are as following.
Signal Name
+RED5
+RED4
+RED3
+RED2
+RED1
+RED0
+GREEN 5
+GREEN 4
+GREEN 3
+GREEN 2
+GREEN 1
+GREEN 0
+BLUE 5
+BLUE 4
+BLUE 3
+BLUE 2
+BLUE 1
+BLUE 0
-DTCLK
Description
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
(Red-pixel Data)
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
(Green-pixel Data)
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
(Blue-pixel Data)
Data Clock
DSPTMG
Display Timing
Red-pixel Data
Each red pixel's brightness data consists of these 6 bits
pixel data.
Green-pixel Data
Each green pixel's brightness data consists of these 6 bits
pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of these 6 bits
pixel data.
The typical frequency is 71.1 MHz. The signal is used to
strobe the pixel data and DSPTMG signals. All pixel data
shall be valid at the falling edge when the DSPTMG signal
is high.
This signal is stored at the falling edge of -DTCLK. When
the signal is high, the pixel data shall be valid to be
displayed.
(C) Copyright AU Optronics
Dec., 2003 All Rights Reserved.
No Reproduction and Redistribution Allowed.
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