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PDF SAF82526 Data sheet ( Hoja de datos )

Número de pieza SAF82526
Descripción High-Level Serial Communication Controller Extended
Fabricantes Siemens 
Logotipo Siemens Logotipo



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Data Communications ICs
High-Level Serial Communication
Controller Extended (HSCX)
SAB 82525; SAB 82526
SAF 82525; SAF 82526
User’s Manual 10.94

1 page




SAF82526 pdf
General Information
The SAB 82525 is a High-Level Serial Communication Controller compatible to the SAB 82520
HSCC with extended features and functionality (HSCX).
The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC channel
(channel B).
The HSCX has been designed to implement high-speed communication links using HDLC
protocols and to reduce the hardware and software overhead needed for serial synchronous
communications.
Due to its 8-bit demultiplexed adaptive bus interface it fits perfectly into every Siemens/Intel or
Motorola 8- or 16-bit microcontroller or microprocessor system. The data through-put from/to
system memory is optimized transferring blocks of data (usually 32 bytes) by means of DMA
or interrupt request. Together with the storing capacity of up to 64 bytes in on-chip FIFO’s, the
serial interfaces are effectively decoupled from the system bus which drastically reduces the
dynamic load and reaction time of the CPU.
The HSCX directly supports the X.25 LAPB, the ISDN LAPD, and SDLC (normal response
mode) protocols and is capable of handling a large set of layer-2 protocol functions
independently from the host processor.
Furthermore, the HSCX opens a wide area for applications which use time division multiplex
methods (e.g. time-slot oriented PCM systems, systems designed for packet switching, ISDN
applications) by its programmable telecom-specific features.
The HSCX is fabricated using Siemens advanced ACMOS 3 technology and available in a
P-LCC-44 pin package.
The data link controller handles all functions necessary to establish and maintain an HDLC
data link, such as
– Flag insertion and detection,
– Bit stuffing,
– CRC generation and checking,
– Address field recognition.
Associated with each serial channel is a set of independent command and status registers
(SP-REG) and 64-byte deep FIFO’s for transmit and receive direction.
DMA capability has been added to the HSCX by means of a 4-channel DMA interface
(SAB 82525) with one DMA request line for each transmitter and receiver of both channels.
General
Advanced CMOS technology
Low power consumption: active 25 mW at 4 MHz
standby 4 mW
Semiconductor Group
5

5 Page





SAF82526 arduino
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
P-LCC P-MQFP
9 14
16 21
RXDA
RXDB
10 15
15 20
RTSA
RTSB
11 16
14 19
CTSA/
CXDA
CTSB/
CXDB
12 17
13 18
TXDA
TXDB
17 22 RES
Input (I) Function
Output (O)
I Receive Data (channel A/channel B)
Serial data is received on these pins at standard TTL or
CMOS levels.
O Request to Send (channel A/channel B)
When the RTS bit in the mode register is set, the RTS
signal goes low. When the RTS is reset, the signal goes
high if the transmitter has finished and there is no further
request for a transmission.
In a bus configuration, this pin can be programmed via
CCR2 to:
– go low during the actual transmission of a frame shifted
by one clock period, excluding collision bits
– go low during the reception of a data frame
– stay always high (RTS disabled).
I Clear to Send (channel A/channel B)
A low on the CTS inputs enables the respective transmitter.
Additionally, an interrupt may be issued if a state transition
occurs at the CTS pin (programmable feature). If no "Clear
To Send" function is required, the CTS inputs can be
connected directly to VSS.
Collision Data (channel A/channel B)
In a bus configuration, the external serial bus must be
connected to the respective C × D pin for collision
detection.
O Transmit Data (channel A/channel B)
Transmit data is shifted out via these pins at standard TTL
or CMOS levels. These pins can be programmed to work
either as push-pull, or open drain outputs supporting bus
configurations.
I RESET
A high signal on this input forces the HSCX into the reset
state. The HSCX is in power-up mode during reset and in
power-down mode after reset. The minimum pulse width is
1.8 µs.
Semiconductor Group
11

11 Page







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