AT89LP428 Hoja de datos PDF

PDF AT89LP428 Datasheet ( Hoja de datos )

Número de pieza AT89LP428
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT89LP428 datasheet

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AT89LP428 pdf
2. Overview
The AT89LP428/828 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K
bytes of In-System Programmable Flash program memory and 512/1024 bytes of Flash data
memory. The device is manufactured using Atmel®'s high-density nonvolatile memory technol-
ogy and is compatible with the industry-standard MCS51 instruction set. The AT89LP428/828 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP428/828 CPU, instructions need only 1 to 4 clock
cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of
instructions need only as many clock cycles as they have bytes to execute, and most of the
remaining instructions require only one additional clock. The enhanced CPU core is capable of
20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current
consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP428/828 provides the following standard features: 4K/8K bytes of In-System
Programmable Flash program memory, 512/1024 bytes of Flash data memory, 768 bytes of
RAM, up to 30 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable
watchdog timer, two analog comparators, a full-duplex serial port, a serial peripheral interface,
an internal RC oscillator, on-chip crystal oscillator, and a four-level, ten-vector interrupt system.
A block diagram is shown in Figure 2-1 on page 6.
Timer 0 and Timer 1 in the AT89LP428/828 are enhanced with two new modes. Mode 0 can be
configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters may independently drive an 8-bit preci-
sion pulse width modulation output.
Timer 2 on the AT89LP428/828 serves as a 16-bit time base for a 4-channel
Compare/Capture Array with up to four multi-phasic, variable precision PWM outputs.
The enhanced UART of the AT89LP428/828 includes Framing Error Detection and Automatic
Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emula-
tion of half-duplex SPI or 2-wire interfaces.
The I/O ports of the AT89LP428/828 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-only mode,
the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode
provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an inter-
rupt using the General-purpose Interrupt (GPI) interface.

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AT89LP428 arduino
In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set. While SIGEN is
one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped
from addresses 0080H to 00FFH and the Atmel Signature Array is mapped from addresses
0000H to 003FH. SIGEN must be cleared before using MOVC to access the code memory. The
User Signature Array may also be modified by the In-Application Programming interface. When
IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access the array.
3.2 Internal Data Memory
The AT89LP428/828 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O
memory mapped into a single 8-bit address space. Access to the internal data memory does not
require any configuration. The internal data memory has three address spaces: DATA, IDATA
and SFR; as shown in Figure 3-2.
Figure 3-2. Internal Data Memory Map
by Indirect
7F H
by Direct and
Indirect Addressing
by Direct
Status and Control Bits
Stack Pointer
3.2.1 DATA
3.2.2 IDATA
3.2.3 SFR
The first 128 bytes of RAM are directly addressable by an 8-bit address (00H - 7FH) included in
the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers
each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc-
tions using register addressing will only access the currently specified bank.
The full 256 bytes of internal RAM can be indirectly addressed using the 8-bit pointers R0 and
R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in
the IDATA space.
The upper 128 direct addresses (80H - FFH) access the I/O registers. I/O registers on AT89LP
devices are referred to as Special Function Registers. The SFRs can only be accessed through
direct addressing. All SFR locations are not implemented. See “Special Function Registers” on
page 15.
10 AT89LP428/828

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