PDF AT89LP428 Datasheet ( Hoja de datos )

Número de pieza AT89LP428
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
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AT89LP428 datasheet

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AT89LP428 pdf
2. Overview
The AT89LP428/828 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K
bytes of In-System Programmable Flash program memory and 512/1024 bytes of Flash data
memory. The device is manufactured using Atmel®'s high-density nonvolatile memory technol-
ogy and is compatible with the industry-standard MCS51 instruction set. The AT89LP428/828 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP428/828 CPU, instructions need only 1 to 4 clock
cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of
instructions need only as many clock cycles as they have bytes to execute, and most of the
remaining instructions require only one additional clock. The enhanced CPU core is capable of
20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current
consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP428/828 provides the following standard features: 4K/8K bytes of In-System
Programmable Flash program memory, 512/1024 bytes of Flash data memory, 768 bytes of
RAM, up to 30 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable
watchdog timer, two analog comparators, a full-duplex serial port, a serial peripheral interface,
an internal RC oscillator, on-chip crystal oscillator, and a four-level, ten-vector interrupt system.
A block diagram is shown in Figure 2-1 on page 6.
Timer 0 and Timer 1 in the AT89LP428/828 are enhanced with two new modes. Mode 0 can be
configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters may independently drive an 8-bit preci-
sion pulse width modulation output.
Timer 2 on the AT89LP428/828 serves as a 16-bit time base for a 4-channel
Compare/Capture Array with up to four multi-phasic, variable precision PWM outputs.
The enhanced UART of the AT89LP428/828 includes Framing Error Detection and Automatic
Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emula-
tion of half-duplex SPI or 2-wire interfaces.
The I/O ports of the AT89LP428/828 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-only mode,
the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode
provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an inter-
rupt using the General-purpose Interrupt (GPI) interface.

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AT89LP428 arduino
3.3 External Data Memory
AT89LP microcontrollers support a 16-bit external data memory address space. The external
memory space is accessed with the MOVX instructions. The AT89LP428/828 does not support
an external memory interface. However, some internal data memory resources are mapped into
portions of the external address space as shown in Figure 3-3. These memory spaces may
require configuration before the CPU can access them. The AT89LP428/828 includes 512 bytes
of on-chip Extra RAM (EDATA) and 512/1024 bytes of nonvolatile Flash data memory (FDATA).
Figure 3-3. External Data Memory Map
3.3.1 EDATA
Flash Data
Extra RAM
Flash Data
Extra RAM
The Extra RAM is a portion of the external memory space implemented as an internal 512-byte
auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external
memory address space, from 0000H to 01FFH. MOVX instructions to this address range will
access the internal Extra RAM. EDATA can be accessed with both 16-bit (MOVX @DPTR) and
8-bit (MOVX @Ri) addresses. When 8-bit addresses are used, the PAGE register (086H) sup-
plies the upper address bits. The PAGE register breaks EDATA into two 256-byte pages. A page
cannot be specified independently for MOVX @R0 and MOVX @R1. When 16-bit addresses are
used (DPTR), the IAP bit (MEMCON.7) must be zero to access EDATA. MOVX instructions to
EDATA require a minimum of 2 clock cycles.
Table 3-3. PAGE – EDATA Page Register
PAGE = 86H
Reset Value = XXXX XXX0B
Not Bit Addressable
– – – – – – – PAGE.0
Bit 7 6 5 4 3 2 1
Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions.

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