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PDF NL160120AC27-05 Data sheet ( Hoja de datos )
| Número de pieza | NL160120AC27-05 | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL160120AC27-05
54cm (21.3 Type)
UXGA
LVDS Interface (2 ports)
DATA SHEET
DOD-PD-1233 (4th edition)
This DATA SHEET is updated document from
DOD-PD-1103(3).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-1233 (4th edition)
Published date: November 2005 CP(N)
1 © NEC LCD Technologies, Ltd.
2004, 2005 All rights reserved.
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NL160120AC27-05
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
432.0 (H) × 324.0 (V) mm
54 cm (21.3 inches)
a-Si TFT active matrix
16,777,216 colors
1,600 (H) × 1,200 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.090 (H) × 0.270 (V) mm
0.270 (H) × 0.270 (V) mm
457.0 (W) × 350.0 (H) × 34.0 (D) mm (typ.)
2,610 g (typ.)
450:1 (typ.)
At the contrast ratio ≥ 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ=2.2): normal axis
(perpendicular)
Antiglare
2H (min.) [by JIS K5400]
Color gamut
At LCD panel center
72% (typ.) [against NTSC color space]
Response time
Ton+Toff (10%←→ 90%)
16 ms (typ.)
Luminance
Signal system
Power supply voltage
At the maximum luminance control
450 cd/m2 (typ.)
2 ports LVDS interface (THC63LVD824 THine Electronics, Inc. or
equivalent)
[RGB 8-bit signals, Data enable signal (DE), Dot clock (CLK)]
LCD panel signal processing board: 12.0V
Inverter: 12.0V
Direct light type: 16 cold cathode fluorescent lamps with inverter
Backlight
Replaceable parts
• Inverter: Type No. 213PW031
Power consumption
The maximum luminance control, Checkered flag pattern
63.7 W (typ.)
DATA SHEET DOD-PD-1233 (4th edition)
5
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NL160120AC27-05
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VDD
Note1
VDD ON
10.8V
0V
0.1ms < Tr < 80ms
VDD OFF
9.6V 10.8V
VDD dip < 20ms
VDD ON
10.8V
Toff > 200ms
LVDS Signals *1,*2
Note2
0V
CS, SDATI, SCLK
Note2
0V
VALID period
t ≥ 20ms Note3
VALID period
10ms < t < 35ms
10ms < t < 35ms
0ms < t < 35ms
☆
*1: LVDS signals: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/- and CKB+/-
*2: LVDS signals should be measured at the terminal of 100Ω resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a
protection circuit may work, and then this product may not work.
Note2: LVDS signals and CS, SDATI, SCLK must be Low or High-impedance, exclude the
VALID period (See above sequence diagram), in order to avoid that internal circuits is
damaged.
If some of signals are cut while this product is working, even if the signal input to it once
again, it might not work normally. VDD should be cut when the display and function
signals are stopped.
Note3: At the beginning of the serial communication mode, take 20ms or more after the LVDS
signal input. When writing and reading the LUT data, see “4.11 TEN-bit LOOK UP
TABLE FOR GAMMA ADJUSTMENT”.
DATA SHEET DOD-PD-1233 (4th edition)
11
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