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PDF CED61A3 Data sheet ( Hoja de datos )
| Número de pieza | CED61A3 | |
| Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Chino-Excel Technology | |
| Logotipo |  |
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CED61A3/CEU61A3
Jan. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
30V , 40A , RDS(ON)=13.5mΩ @VGS=10V.
6 RDS(ON)=20m Ω @VGS=4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-251 & TO-252 package.
D
G
G
S
CEU SERIES
TO-252AA(D-PAK)
G
DS
CED SERIES
TO-251(l-PAK)
D
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
VDS
VGS
ID
IDM
IS
PD
TJ, TSTG
Limit
30
Ć20
40
120
40
50
0.4
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
6-62
2.5
50
C/W
C/W
1 page  
CED61A3/CEU61A3
4
VDD
ton toff
RL
VIN
D
VOUT
td(on)
tr td(off)
90%
tf
90%
VGS
VOUT
10% INVERTED
10%
6 RGEN G
90%
S
VIN 50%
50%
10%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
2
1
D=0.5
0.2
0.1
0.1 0.05
0.02
0.01
Single Pulse
0.01
0.01
0.1
1 10 100
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
1000
10000
Figure 13. Normalized Thermal Transient Impedance Curve
6-66
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CED61A3.PDF ] | |
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