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PDF A32140DX Data sheet ( Hoja de datos )

Número de pieza A32140DX
Descripción Integrator Series FPGAs
Fabricantes Actel 
Logotipo Actel Logotipo



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Integrator Series FPGAs:
1200XL and 3200DX Families
Discontinued – v3.0
Features
High Capacity
• 2,500 to 30,000 Logic Gates
• Up to 3Kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 250 User-Programmable I/O Pins
High Performance
• 225 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
Ease-of-Integration
• Synthesis-Friendly Architecture Supports ASIC Design
Methodologies.
• 95–100% Device Utilization using Automatic
Place-and-Route Tools.
• Deterministic, User-Controllable Timing Via Timing
Driven Software Tools with Up To 100% Pin Fixing.
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.
General Description
Actel’s Integrator Series FPGAs are the first programmable
logic devices optimized for high-speed system logic
integration. Based on Actel’s proprietary antifuse
technology and 0.6-micron double metal CMOS process,
Integrator Series devices offer a fine-grained, register-rich
architecture with embedded dual-port SRAM and
wide-decode circuitry.
Integrator Series’ 3200DX and 1200XL families were
designed to integrate system logic which is typically
implemented in multiple CPLDs, PALs, and FPGAs. These
devices provide the features and performance required for
today’s complex, high-speed digital logic systems. The
3200DX family offers fast dual-port SRAM for implementing
FIFOs, LIFOs, and temporary data storage. The large
number of storage elements can efficiently address
applications requiring wide datapath manipulation and
transformation functions such as telecommunications,
networking, and DSP.
Integrator Series Product Profile Family
Device
Capacity
Logic Gates1
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Clocks
User I/O (Maximum)
JTAG
A1225XL
2,500
N/A
231
220
N/A
N/A
231
2
83
No
1200XL
A1240XL
4,000
N/A
348
336
N/A
N/A
348
2
104
No
A1280XL
8,000
N/A
624
608
N/A
N/A
624
2
140
No
A3265DX
6,500
N/A
510
475
20
N/A
510
2
126
No
Packages
PL84
PQ100
VQ100
PG100
PL84 PQ100
PQ144
TQ176
PG132
PL84
PQ160 PQ208
TQ176
PG176 CQ172
Note: Logic gate capacity does not include SRAM bits as logic.
PL84
PQ100
PQ160
TQ176
A32100DX
3200DX
A32140DX
A32200DX
A32300DX
10,000
2,048
700
662
20
8
700
6
152
Yes
PL84
PQ160
PQ208
TQ176
CQ84
14,000
N/A
954
912
24
N/A
954
2
176
Yes
PL84
PQ160
PQ208
TQ176
CQ256
20,000
2,560
1,230
1,184
24
10
1,230
6
202
Yes
PQ208
RQ208
RQ240
CQ208
CQ256
30,000
3,072
1,888
1,833
28
12
1,888
6
250
Yes
RQ208
RQ240
CQ256
February 2001
© 2001 Actel Corporation
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A32140DX pdf
Integrator Series FPGAs: 1200XL and 3200DX Families
Development Tool Support
The devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage, Actel’s suite of FPGA development
point tools for PCs and Workstations, includes the ACTgen
Macro Builder, timing-driven place and route and analysis
tools, and device programming software.
In addition, the devices contain ActionProbe circuitry that
provides built-in access to every node in a design, enabling
100 percent real-time observation and analysis of a device's
internal logic nodes without design iteration. The probe
circuitry is accessed by Silicon Explorer II, an easy-to-use
integrated verification and logic analysis tool that can
sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
Integrator Series Architectural
Overview
The 1200XL and 3200DX architecture is composed of
fine-grained building blocks which produce fast, efficient
logic designs. All devices within the Integrator Series are
composed of logic modules, routing resources, clock
networks, and I/O modules which are the building blocks to
design fast logic designs. In addition, a subset of devices
contain embedded dual-port SRAM and wide-decode
modules. The dual-port SRAM modules are optimized for
high-speed datapath functions such as FIFOs, LIFOs, and
scratchpad memory. The “Integrator Series Product Profile
Family” on page 1 lists the specific logic resources
contained within each device.
Plastic Device Resources
User I/Os
Device
PLCC 84-Pin VQFP 100-Pin
PQFP
100-Pin
PQFP 144-Pin PQFP 160-Pin PQFP 208-Pin
RQFP
240-Pin
TQFP 176-Pin
A1225XL
72 83 83 — — — — —
A1240XL
72 — 83 104 — — — 103
A3265DX
72 — 83 — 125 — — 126
A1280XL
72 — — — 125 140 — 140
A32100DX
72 — — — 125 152 — 142
A32140DX
72 — — — 125 176 — 150
A32200DX
176*
202
A32300DX
— — — — — 176 202 —
Package Definitions (Consult your local Actel Sales Representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array, VQFP = Very Thin Quad Flat
Pack, RQFP = Plastic Power Quad Flat Pack
* Also available in RQFP 208-pin.
Hermetic Device Resources
User I/Os
Device
CPGA
176-Pin
CQFP
84-Pin
CQFP
172-Pin
A1280XL
140 — 140
A32100DX
— 60 —
A32140DX
———
A32200DX
———
A32300DX
———
Package Definitions (Consult your local Actel Sales Representative for product availability.)
CPGA = Ceramic Pin Grid Array, CQFP = Ceramic Quad Flat Pack
CQFP
208-Pin
176
CQFP
256-Pin
176
202
212
Discontinued – v3.0
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A32140DX arduino
Integrator Series FPGAs: 1200XL and 3200DX Families
Table 1 • IEEE 1149.1 BST Signals
Signal
TDI
TDO
TMS
TCK
Name
Function
Test Data In
Serial data input for BST instructions and
data. Data is shifted in on the rising edge
of TCK.
Test Data Out
Serial data output for BST instructions
and test data.
Test Mode Select
Serial data input for BST mode. Data is
shifted in on the rising edge of TCK.
Test Clock
Clock signal to shift the BST data into
the device.
JTAG
All 3200DX devices are IEEE 1149.1 (JTAG) compliant.
3200DX devices offer superior diagnostic and testing
capabilities by providing JTAG and probing capabilites.
These functions are controlled through the special JTAG
pins in conjunction with the program fuse.
JTAG fuse programmed:
• TCK must be terminated—logical high or low doesn’t
matter (to avoid floating input)
• TDI, TMS may float or at logical high (internal pull-up is
present)
• TDO may float or connect to TDI of another device (it’s an
output)
JTAG fuse not programmed:
• TCK, TDI, TDO, TMS are user I/O. If not used, they will be
configured as tristated output.
BST Instructions
Boundary scan testing within the 3200DX devices is
controlled by a Test Access Port (TAP) state machine. The
TAP controller drives the three-bit instruction register, a
bypass register, and the boundary scan data registers within
the device. The TAP controller uses the TMS signal to
control the testing of the device. The BST mode is
determined by the bitstream entered on the TMS pin.
Table 2 describes the test instructions supported by the
3200DX devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCLK signals. An active
reset (nTRST) pin is not supported; however, the 3200DX
contains power-on circuitry which automatically resets the
BST circuitry upon power-up. The following table
summarizes the functions of the BST signals.
Table 2 • BST Instructions
Test Mode
EXTEST
SAMPLE/
PRELOAD
JPROBE
USER
INSTRUCTION
HIGH Z
CLAMP
BYPASS
Code
000
001
011
100
101
110
111
Description
Allows the external circuitry and
board-level interconnections to be tested
by forcing a test pattern at the output pins
and capturing test results at the input
pins.
Allows a snapshot of the signals at the
device pins to be captured and examined
during device operation.
A private instruction allowing the user to
connect Actel’s Micro Probe registers to
the test chain.
Allows the user to build
application-specific instructions such as
RAM READ and RAM WRITE.
Refer to the IEEE Standard 1149.1
specification.
Refer to the IEEE Standard 1149.1
specification.
Enables the bypass register between the
TDI and TDO pins. The test data passes
through the selected device to adjacent
devices in the test chain.
JTAG BST Instructions
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the JTAG testing of the device. The JTAG test mode is
determined by the bitstream entered on the TMS pin. The
table in the next column describes the JTAG instructions
supported by the 3200DX.
Design Tool Support ActionProbe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic
or I/O module output can be observed in real time using the
ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s
Silicon Explorer diagnostic and debug tool kit.
Discontinued – v3.0
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