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PDF TDA8060ATS Data sheet ( Hoja de datos )
| Número de pieza | TDA8060ATS | |
| Descripción | Satellite ZERO-IF QPSK down-converter | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8060ATS
Satellite ZERO-IF QPSK
down-converter
Product specification
File under Integrated Circuits, IC02
2000 Nov 10
1 page  
Philips Semiconductors
Satellite ZERO-IF QPSK down-converter
Product specification
TDA8060ATS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VCC
Vi(max)
tsc(max)
Tamb
Tstg
Tj
PARAMETER
supply voltage
maximum input voltage on all pins
maximum short-circuit time
ambient temperature
storage temperature
junction temperature
MIN.
−0.3
−0.3
−
−20
−55
−
MAX.
+6.0
VCC
10
+85
+150
150
UNIT
V
V
s
°C
°C
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth(j-a)
thermal resistance from junction to ambient
CONDITIONS
in free air
VALUE
120
UNIT
K/W
DC CHARACTERISTICS
VCC = 4.75 to 5.25 V; Tamb = −20 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VCC supply voltage
ICC supply current
PEN = 5 V
PEN = 0 V
Conversion stage
VI(RFA)
DC input voltage on pin RFA
VI(RFB)
DC input voltage on pin RFB
VO(IOUT)
DC output voltage on pin IOUT
VO(QOUT) DC output voltage on pin QOUT
Quadrature generator
VO(LOOUT) DC output voltage on pin LOOUT
VO(LOOUTC) DC output voltage on pin LOOUTC
Baseband stage
VI(IBBIN)
VI(QBBIN)
VO(IBBOUT)
VO(QBBOUT)
DC input voltage on pin IBBIN
DC input voltage on pin QBBIN
DC output voltage on pin IBBOUT
DC output voltage on pin QBBOUT
MIN.
4.75
73
70
−
−
−
−
−
−
−
−
−
−
TYP.
5.00
83
80
0.9
0.9
1.85
1.85
4.0
4.0
2.5
2.5
2.5
2.5
MAX.
5.25
93
90
UNIT
V
mA
mA
−V
−V
−V
−V
−V
−V
−V
−V
−V
−V
2000 Nov 10
5
5 Page 
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LOW-PASS
FILTER(3)
VCC(MIX) MIXGND VCC(RF) RFGND VCC(LO) LOGND
2 4 8 7 17 18
100 nF
VCC(DIV) DIVGND IOUT IBBIN
22 21 15 14
1 pF
RF
(2)
RF
1 pF
gain(1)
RFA 6
RFB 5
AGC 1
LNA
100 nF
CONVERSION STAGE
×
100 MHz
×
100 MHz
I CONVERTER
SYM ASYM
Q CONVERTER
SYM ASYM
AMP
13 IBBOUT
LOW-PASS
FILTER(3)
BASEBAND
STAGE
AMP
12 QBBOUT LOW-PASS
FILTER(3)
to
I channel
ADC
to
Q channel
ADC
0 to 5 V
PEN 3
QUADRATURE
GENERATOR
DIVIDE-BY-2
STABILIZED LO
PLL AND
AMPLIFIER
OSCILLATOR
TDA8060ATS
24 23
LOOUT LOOUTC
19
TKA
6Ω
1 pF
20
TKB
6Ω
to PLL
synthesizer IC
BB835
20 (2×)
kΩ
20
kΩ
10 11
QOUT QBBIN
100 nF
LOW-PASS
FILTER(3)
Vtune
from PLL synthesizer IC
(1) Gain control voltage; minimum gain at 0.1VCC, maximum gain at 0.9VCC; 30 dB range.
(2) Differential RF input 950 to 2200 MHz; level = −22 to −52 dBm per channel.
(3) The filter input impedance is 400 Ω minimum.
Fig.6 Application diagram.
9 VCC(BB)
16 BBGND
FCE415
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TDA8060ATS.PDF ] | |
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