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PDF GN25L95 Data sheet ( Hoja de datos )

Número de pieza GN25L95
Descripción 2.5 Gbps CMOS Burst Mode Laser Driver & Limiting Post Amplifier
Fabricantes Semtech 
Logotipo Semtech Logotipo



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GN25L95
2.5 Gbps CMOS Burst Mode Laser Driver & Limiting Post
Amplifier with On-Chip Digital Diagnostic Monitoring
Main Features
100 mA bias current and 90 mA
modulation current output drive capability
On-chip Digital Diagnostic Monitoring
(DDMI)
Automatic Mean Power and Automatic
Extinction Ratio control
Fast burst-mode loop settling time
Current DAC output for APD bias control
TX_SD and rogue ONU alarm function
True average Tx burst power monitor
Tx fault detection and safety logic
Power down and sleep mode support
CSFP I2C addressing support
Applications
EPON & GPON FTTh ONU/ONT
BOSA-on-Board ONU
SFF/SFP & CSFP modules
General Description
The GN25L95 is a combined burst mode
laser driver and limiting post amplifier
designed for fiber optic transceiver modules.
The GN25L95 features on-chip digital
diagnostic monitoring and digital set-up. This
enables a complete solution for SFP/SFF
optical transceiver modules.
A fully compliant SFF-8472 digital
diagnostic monitoring solution can be
realised by connecting an external 8k
EEPROM.
The GN25L95 features automatic mean
power and automatic extinction ratio control
functions for robust and reliable control of
laser operating conditions over temperature.
Auto-ranging A/D converters with digitized
monitoring, an internal temperature sensor
and an on-chip DAC for controlling an
external APD bias circuit are also included.
Consuming 90 mA from a 3.3 V supply the
GN25L95 is packaged in a 4x4 mm QFN 28
pin RoHS package rated from -40 to +95 °C.
Block Diagram
Package
VCC_TX VCC_RX VCC_DIG LOS/SD
RXOUT+
RXOUT-
BEN+
BEN-
CML
BURST
ENABLE
Limiter
LOS
&
Filter
RXIN+
Gain
RXIN-
APD
DAC
APD_DAC
TXIN+
TXIN-
RX_SLEEP
SDA
SCL
EE_SDA
EE_SCL
DATA
INPUT
STATE MACHINE
DDMI
CONTROLLER
NVM
DIGITAL
INTERFACE
EEPROM
CONTROLLER
MOD
DRIVER
APC & AUTO ER CONTROL
BIAS
DRIVER
Burst
Mean
Power
Monitor
SAFETY LOGIC &
CONTROL
TX
SD
DIGITAL
ADC &
TEMP
SENSOR
LASER+
LASER-
BIAS+
BIAS-
TX_SD
MPD
RSSI_IN
ADC_IN
GND TX_DISABLE/ TX_FAULT
TX_SLEEP
28 27 26 25 24 23 22
SD/LOS 1
21 TX_SD
RXOUT- 2
20 TX_FAULT
RXOUT+ 3
VCC_DIG 4
GN25L95
19 LASER+
18 LASER-
SDA 5
17 VCC_TX
SCL 6
16 BIAS+
EE_SDA 7
15 BIAS-
8 9 10 11 12 13 14
Figure 1 – GN25L95 Functional Block diagram
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
www.semtech.com
Figure 2 – GN25L95 Package
1
Proprietary & Confidential

1 page




GN25L95 pdf
Figure 59 – I2C Address Decoding........................................................................................................ 69
Figure 60 – I2C Write Transaction......................................................................................................... 70
Figure 61 – I2C Read Transaction......................................................................................................... 71
Figure 62 – GN25L95 Register & Memory Structure ............................................................................ 74
Figure 63 – GN25L95 Burst Tx Power Monitor Functional Diagram .................................................... 80
Figure 64 – GN25L95 RSSI Monitor A/D Input ..................................................................................... 81
Figure 65 – GN25L95 A0h Memory Map .............................................................................................. 84
Figure 66 – GN25L95 A2h Memory Map .............................................................................................. 85
Figure 67 – Typical EPON Module Application Using GN25L95 ........................................................ 112
Figure 68 – Typical GPON Module Application Using GN25L95........................................................ 113
Figure 69 – Typical GPON ONU BOSA-on-Board Application Using GN25L95 ................................ 114
Figure 70 – Typical SFP DDMI Module Application Using GN25L95 ................................................. 115
Figure 71 – 4 mm x 4 mm QFN 28 Lead Mechanical Package Drawing............................................ 116
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
5
Proprietary & Confidential

5 Page





GN25L95 arduino
Symbol
Parameter
VSQU_EN
Differential output voltage, pk-pk
(squelched)
Receiver Signal Detect Stage
VLOS
HYS
LOS programming range [7]
LOS Hysteresis programmable
Range (optical) [8]
VARTHRESH
SDASSERT
SDDE-ASSERT
LOS/SD threshold variation [9]
LOS/SD assert time [10]
LOS/SD de-assert time [10]
Receiver APD DAC Control
Min.
Typ.
Max.
10
Units
mV
10.0
0.5
-0.5
2.3
2.3
60.0
3.0
+0.5
100
100
mV
dB
dB
µs
µs
APDSOURCE Full scale DAC source current [11]
1980
µA
APDSINK
Full scale DAC sink current [12]
495 µA
APDSRC_ACC DAC source ouput accuracy
±4 %
APDSNK_ACC DAC sink output accuracy
±4 %
APDSRC_CP APD output compliance (sinking)
0.8 V
APDSNK_CP APD output compliance (sourcing)
VCC-0.8
V
[1] Input sensitivity and overload specified for a BER = 1E-10 and a PRBS 223-1 at 2.5 Gbps.
[2] Differential pk-to-pk output amplitude swing. Measured using a 11110000 square wave pattern. 1000 mVpp setting not
advised for use above 622 Mbps.
[3] Measured using a 11110000 square wave for receiver settings shown in Table 25. Between 20%-80% levels.
[4] Duty cycle distortion value specified (measured differentially) is valid at 2.5Gbps.
[5] Deterministic jitter measured with a 27-1 PRBS + 80 consecutive ones + 27-1 PRBS + 80 consecutive zeros at 2.5 Gbps.
Input amplitudes > 20mVpp differential swing.
[6] Random jitter measured with a 1010 test pattern at 2.5 Gbps. input amplitudes > 20 mVpp differential swing.
[7] Differential input. Equivalent to the optical modulation amplitude. Within the specified range the actual LOS level is within 0.5
dB of the target programmed LOS level. The LOS programming range stated is for hysteresis values of 2.5 dB and below. With
3 dB hysteresis the programming range is reduced to 50 mVpp.
[8]
HYSOptical
=
10
×
log10

VLOS
VLOS _
_ ASSERT
DEASSERT
 , LOS Hysteresis can be set by user to 0.5, 1,1.5, 2, 2.5 or 3 dB
optical.
[9] Valid across operating temperature range, supply voltage range and wafer fabrication process corners.
[10] LOS timing measured using open drain LOS output into a 10k Ω resistor pull-up to VCC. From LOSASSERT threshold +1dB
to overload.
[11] APD DAC output has two ranges when used in source mode: 0-1980 µA and 0-990 µA. See page 66 for details.
[12] APD DAC output has two ranges when used in sink mode: 0-495 µA and 0-247.5 µA. See page 66for details.
Table 7 – Digital Monitoring & Interface Section Characteristics
Symbol
Parameter
Min. Typ.
Max.
Digital Diagnostic Monitoring Functions
TRANGE
TACC
Temperature sensor range [1]
Temperature absolute accuracy
- 40
±2
+ 95
±3
Units
°C
°C
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
11
Proprietary & Confidential

11 Page







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