PDF IDT8P34S1208I Data sheet ( Hoja de datos )

Número de pieza	IDT8P34S1208I
Descripción	1:8 LVDS Output 1.8V Fanout Buffer
Fabricantes	Integrated Device
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No Preview Available ! 1:8 LVDS Output 1.8V Fanout Buffer IDT8P34S1208I DATA SHEET General Description The IDT8P34S1208I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8P34S1208I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8P34S1208I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Features • Eight low skew, low additive jitter LVDS output pairs • Two selectable, differential clock input pairs • Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • LVCMOS/LVTTL interface levels for the control input select pin • Output skew: 20ps (typical) • Propagation delay: 315ps (typical) • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 41fs (typical) • Full 1.8V supply voltage • Lead-free (RoHS 6), 28-Lead VFQFN packaging • -40°C to 85°C ambient operating temperature Block Diagram. VREF0 CLK0 nCLK0 Voltage Reference VDD CLK1 nCLK1 VDD fREF SEL VREF1 Voltage Reference Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Pin Assignment 21 20 19 18 17 16 15 Q4 22 IDT8P34S1208I 14 GND nQ4 23 28-lead VFQFN 13 nQ0 Q5 24 5.0mm x 5.0mm x 0.75mm 12 Q0 package body nQ5 25 11 VREF0 Q6 26 3.25mm x 3.25mm ePad Size 10 nCLK0 nQ6 27 NB Package 9 CLK0 VDD 28 Top View 8 VDD 1234567 IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 1 ©2014 Integrated Device Technology, Inc. 1 page IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER AC Electrical Characteristics Table 5. AC Electrical Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85° Note 1. Symbol Parameter Test Conditions Minimum Typical Maximum Units fREF Input CLK[0:1], Frequency nCLK[0:1] 1.2 GHz V/t Input CLK[0:1], Edge Rate nCLK[0:1] 1.5 V/ns tPD tsk(o) Propagation DelayNote 2. Output SkewNote 3. Note 4. CLK[0:1]; nCLK[0:1] to any Qx, nQx for VPP = 0.4V 190 315 400 ps 20 40 ps tsk(i) Input Skew 10 45 ps tsk(p) tsk(pp) Pulse Skew Part-to-Part SkewNote 5. fREF = 100MHz 6 20 ps 250 ps fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 1kHz – 40MHz 122 221 fs fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 10kHz – 20MHz 88 110 fs fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 12kHz – 20MHz 84 110 fs Buffer Additive Phase fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 1kHz – 40MHz tJIT Jitter, RMS; refer to Additive Phase Jitter fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 10kHz – 20MHz Section fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 12kHz – 20MHz 57 107 fs 41 78 fs 41 78 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 1kHz – 40MHz 55 112 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 10kHz – 20MHz 40 85 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 12kHz – 20MHz 40 85 fs tR / tF Output Rise/ Fall Time 10% to 90% outputs loaded with 100  20% to 80% outputs loaded with 100  305 400 ps 175 260 ps MUXISOLATION Mux IsolationNote 6. fREF = 100MHz 80 dB 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi- librium has been reached under these conditions. 2. Measured from the differential input crossing point to the differential output crossing point 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. 4. This parameter is defined in accordance with JEDEC Standard 65. 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 6. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section. IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 5 ©2014 Integrated Device Technology, Inc. 5 Page IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER 1.8V Differential Clock Input Interface The CLK /nCLK accepts LVDS and other differential signals. The differential input signal must meet both the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the CLK /nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. Differential Input Driven by an LVDS Driver - DC Coupling Figure 2B. Differential Input Driven by an LVPECL Driver - AC Coupling Figure 2C. Differential Input Driven by an LVDS Driver - AC Coupling Figure 2D. Differential Input Driven by a CML Driver IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 11 ©2014 Integrated Device Technology, Inc. 11 Page

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