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PDF NCP5378 Data sheet ( Hoja de datos )
| Número de pieza | NCP5378 | |
| Descripción | Single Phase Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5378
Single Phase Synchronous
Buck Controller with
Integrated Gate Drivers and
Programmable DAC
The NCP5378 is a single chip solution which combines differential
voltage sensing, differential phase current sensing, adaptive voltage
positioning, and on board gate drivers to provide accurately regulated
power for Intel processors. This controller IC maintains the same
features as the multi−phase product family, but reduces the output to a
single−phase, for lower current systems. Low power mode operation
combined with inductor current sensing reduces system cost by
providing the fastest initial response to dynamic load events.
The gate drive adaptive non overlap and power saving operation
circuit can provide a low switching loss and high efficiency solution
for notebook and desktop systems. A high performance operational
error amplifier is provided to simplify compensation of the system.
Dynamic Reference Injection further simplifies loop compensation by
eliminating the need to compromise between closed−loop transient
response and Dynamic VID performance.
Features
• Meets Intel’s VR11.1 Specifications
• High Performance Operational Error Amplifier
• Internal Soft Start
• Dynamic Reference Injection (Patent #US07057381)
• DAC Range from 0.5 V to 1.6 V
• ±0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V
• True Differential Remote Voltage Sensing Amplifier
• “Lossless” Differential Inductor Current Sensing
• Adaptive Voltage Positioning (AVP)
• Latched Over Voltage Protection (OVP)
• Guaranteed Startup into Pre−Charged Loads
• Threshold Sensitive Enable Pin for VTT Sensing
• Power Good Output with Internal Delays
• Thermally Compensated Current Monitoring
• Thermal Shutdown Protection
• Adaptive−Non−Overlap Gate Drive Circuit
• Integrated MOSFET Drivers
• Automatic Power−saving Modes Maximize Efficiency during Light
Load Operation
• 32−lead QFN
• This is a Pb−Free Device
Applications
• Desktop Power Supplies for Next−generation Intel Chipsets
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 1
1
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1 32
QFN32
CASE 488AM
MARKING DIAGRAM
1
NCP5378
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
VR_RDY 1
IMON
VSP
VSN
VFB
COMP
QFN−32
(Top View)
DIFFOUT
ILIM
VCC
BST
TG
SWN
VCCP
BG
EN
OFS
ORDERING INFORMATION
Device
Package
Shipping†
NCP5378MNR2G QFN32 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP5378/D
1 page  
NCP5378
ELECTRICAL CHARACTERISTICS
0°C < TA < 70°C; 0°C < TJ < 125°C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted.
Parameter
Test Conditions
Min Typ Max Unit
ERROR AMPLIFIER
Input Bias Current
−200
−
200 nA
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
DIFFERENTIAL SUMMING AMPLIFIER
CL = 60 pF to GND,
RL = 10 kW to GND
CL = 60 pF to GND,
RL = 10 kW to GND
CL = 60 pF to GND,
RL = 10 kW to GND
DVin = 100 mV, G = −10V/V,
DVout = 1.5 V − 2.5 V,
CL = 60 pF to GND,
DC Load = ±125 mA to GND
10 mV of Overdrive,
ISOURCE = 2.0 mA
10 mV of Overdrive,
ISINK = 500 mA
10 mV of Overdrive,
Vout = 3.5 V
10 mV of Overdrive,
Vout = 0.1 V
− 100 − dB
− 18 − MHz
− 70 −
°
− 10 − V/ms
3.0 − − V
− − 75 mV
1.5 2.0 − mA
0.65 1.0 − mA
V+ Input Pull down Resistance
DRVON = low
DRVON = high
− 0.6 − kW
− 6.0 −
V+ Input Bias Voltage
DRVON = low
DRVON = high
− 0.05 0.1
0.8 0.88 0.95
V
Input Voltage Range (Note 3)
−0.3 − 3.0 V
−3 dB Bandwidth
Closed Loop DC gain VS to Diffout (Note 3)
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
INTERNAL OFFSET VOLTAGE
CL = 80 pF to GND,
RL = 10 kW to GND
VS+ to VS− = 0.5 V to 1.6 V
10 mV of Overdrive,
ISOURCE = 2 mA
10 mV of Overdrive,
ISINK = 1 mA
10 mV of Overdrive,
Vout = 3 V
10 mV of Overdrive,
Vout = 0.2 V
− 15 − MHz
0.98 1.0 1.02 V/V
3.0 − − V
− − 0.5 V
1.5 2.0 − mA
1.0 1.5 − mA
Offset Voltage to the (+) Pin of the Error Amp &
the VDRP Pin
−2 0 +2 mV
VDROOP AMPLIFIER
Input Bias Current
−200
−
200 nA
Inverting Voltage Range
0 1.3 3.0 V
Open Loop DC Gain
CL = 20 pF to GND including ESD
RL = 1 kW to GND
− 100 − dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND including ESD
RL = 1 kW to GND
− 18 − MHz
3. Guaranteed by design.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
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5
5 Page 
NCP5378
The comp pin will be pulled to ground in a fault condition
and should not jump up when the fault cleared.
Differential Current Feedback Amplifier
A differential amplifier are provided to sense the output
current of each phase.
The current sense amplifier senses the current through its
corresponding phase. A voltage is generated across a current
sense element such as an inductor or sense resistor. The
sense voltage will be very low. The sense element will
normally be between 0.5 mW and 1.5 mW. It is possible to
sense both negative and positive going current. It is further
possible that the differential sense signal is below 0 V. The
output of these amplifiers shall not invert if the common
mode range is exceeded.
The gain of this amplifier is fixed and is noninverting. The
output of the amplifier is used to control 3 functions. First,
the output controls the adaptive voltage positioning, where
the output voltage is actively controlled according to the
output current. Second, the output signal is fed to the current
limit circuit. Finally, the phase current is connected to the
PWM comparator. The offset voltage difference from
amplifier to amplifier and the error in bias current from
amplifier to amplifier need to be minimized. The offset and
bias current design needs to be able to eliminate differences
from amplifier to amplifier.
Switching Frequency in RPM Mode
When the NCP5378 operates in RPM mode, its switching
frequency is controlled by the ripple voltage on the COMP
pin. Each time the COMP pin voltage exceeds the RPM pin
voltage threshold level determined by the VID voltage and
the external resistor connected between RPM and ground, an
internal ramp signal is started and TG is driven high. The
slew rate of the internal ramp is programmed by the current
entering the ROSC pin. When the internal ramp signal
intercepts the COMP voltage, the TG pin is reset low. In
continuous current mode, the switching frequency of RPM
operation is almost constant. While in discontinuous current
conduction mode, the switching frequency is reduced as a
function of the load current.
Soft Start
Soft start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table.
The VR11 mode ramps DAC to 1.1 V, pauses for 500 ms,
reads the DAC setting, then ramps to the final DAC setting.
Digital Slew Rate Limiter / Soft Start Block
The slew rate limiter and the soft−start block are to be
implemented with a digital up/down counter controlled by
an oscillator that can be synchronized to VID line changes.
During soft start the DAC will ramp at the softstart rate, after
soft start is complete the ramp rate will follow the Intel rate
depending on the mode. In normal operation the design must
keep up with the Intel spec of 1 DAC step every 1.25 ms.
The DAC must be implemented down as close to zero as
possible (less than 20 mV out the DAC Buffer) in order to avoid
the output voltage jumping up at the beginning of the ramp.
Preferably when DAC = 0 the buffer to the RS amp should
deliver less than 20 mV. The digital DAC offset should be
introduced prior to the digital compare.
Protection Features
Undervoltage Lockouts
An undervoltage circuit senses the input VCC and VCCP of
the controller and driver voltage rail. During power up the
input voltage to the controller is monitored. The PWM
outputs and the soft start circuit are disabled until the input
voltage exceeds the threshold voltage of the comparator.
Hysteresis is incorporated within the comparator.
The PWM signals will control the gate status when VCC
threshold is exceeded. If VCC decreases below the stop
threshold, the output gate will be forced low unit input
voltage VCC rises above the startup threshold.
Overcurrent Latch
A programmable overcurrent latch is incorporated within
the IC. The oscillator pin provides the reference voltage for
this pin. A resistor divider from this pin generates the
reference voltage. The latch is set when the current
information exceeds the programmed voltage. To recover
the part must be reset by the EN pin or by cycling VCC.
The outputs will remain disabled until the VCC voltage or
EN is removed and reapplied.
UVLO Monitor
If the output voltage falls greater than 300 mV below the
DAC voltage the UVLO comparator will trip sending the
VR_RDY signal low.
Overvoltage Protection
The output voltage is monitored at the input of the
differential amplifier. During normal operation, if the output
voltage exceeds the DAC voltage by 180 mV (OR 350 mV
if OFS is active), the VR_RDY flag goes low, the high side
gate drivers are all brought low, and the low side gate drivers
are all brought high until the voltage falls below the OVP
threshold. If the over voltage trip 8 times the output voltage
will shut down. The OVP will not shut down the controller
if it occurs during soft−start. This is to allow the controller
to pull the output down to the DAC voltage and start up into
a pre−charged output.
VCCP Power ON Reset OVP
The VCCP power on reset OVP feature is used to protect
the CPU during startup. When VCCP is higher than 3.2 V, the
gate driver will monitor the switching node SW pin. If SWN
pin higher than 1.9 V, the bottom gate will be forced to high
for discharge of the output capacitor. This works best if the
5 V standby is diode OR’ed into VCCP with the 12 V rail. The
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NCP5378.PDF ] | |
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