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Número de pieza | M29W256GL | |
Descripción | Parallel NOR Flash Embedded Memory | |
Fabricantes | Micron Technology | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de M29W256GL (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! 256Mb: 3V Embedded Parallel NOR Flash
Features
Parallel NOR Flash Embedded Memory
M29W256GH, M29W256GL
Features
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65–3.6V (I/O buffers)
– VPPH = 12V for fast program (optional)
• Asynchronous random/page read
– Page size: 8 words or 16 bytes
– Page access: 25ns, 30ns
– Random access: 60ns1, 70ns, 80ns
• Fast program commands: 32-word (64-byte) write
buffer
• Enhanced buffered program commands: 256-word
• Program time
– 16µs per byte/word TYP
– Chip program time: 10s with VPPH and 16s with-
out VPPH
• Memory organization
– Uniform blocks: 256 main blocks, 128KB, or 64-
Kwords each
• Program/erase controller
– Embedded byte/word program algorithms
• Program/erase suspend and resume capability
– Read from any block during a PROGRAM SUS-
PEND operation
– Read or program another block during an ERASE
SUSPEND operation
• Unlock bypass, block erase, chip erase, write to buf-
fer and program
– Fast buffered/batch programming
– Fast block/chip erase
• VPP/WP# pin protection
– Protects first or last block regardless of block
-protection settings
• Software protection
– Volatile protection
– Nonvolatile protection
– Password protection
• Extended memory block
– 128-word (256-byte) memory block for perma-
nent, secure identification
– Programmed or locked at the factory or by the
customer
• Common Flash interface
– 64-bit security code
• Low power consumption: Standby and automatic
mode
• JESD47H-compliant
– 100,000 minimum PROGRAM/ERASE cycles per
block
– Data retention: 20 years (TYP)
• 65nm single-level cell (SLC) process technology
• Fortified BGA, TBGA, and TSOP packages
• "Green" packages available
– RoHS-compliant
– Halogen-free
• Automotive device grade (6) temperature: –40°C to
+85°C (automotive grade-certified)
• Automotive device grade (3) temperature: –40°C to
+125°C (automotive grade-certified)
Note: 1. The 60ns device is available upon customer
request.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page 256Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 8
Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA ............................................................................................. 9
Figure 4: Data Polling Flowchart .................................................................................................................... 16
Figure 5: Toggle Bit Flowchart ........................................................................................................................ 17
Figure 6: Status Register Polling Flowchart ..................................................................................................... 18
Figure 7: Lock Register Program Flowchart ..................................................................................................... 20
Figure 8: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 30
Figure 9: ENHANCED BUFFERED PROGRAM Flowchart ................................................................................ 34
Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 43
Figure 11: Software Protection Scheme .......................................................................................................... 48
Figure 12: Power-Up Timing .......................................................................................................................... 53
Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 54
Figure 14: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 55
Figure 15: AC Measurement Load Circuit ....................................................................................................... 57
Figure 16: AC Measurement I/O Waveform ..................................................................................................... 57
Figure 17: Random Read AC Timing (8-Bit Mode) ........................................................................................... 61
Figure 18: Random Read AC Timing (16-Bit Mode) ......................................................................................... 61
Figure 19: Page Read AC Timing (16-Bit Mode) ............................................................................................... 62
Figure 20: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 64
Figure 21: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 65
Figure 22: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 67
Figure 23: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 68
Figure 24: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 69
Figure 25: Accelerated Program AC Timing ..................................................................................................... 70
Figure 26: Data Polling AC Timing .................................................................................................................. 71
Figure 27: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 71
Figure 28: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 73
Figure 29: 64-Ball TBGA – 10mm x 13mm ....................................................................................................... 74
Figure 30: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 75
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
5 Page 256Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 2: Signal Descriptions (Continued)
Name
VCC
VCCQ
VSS
RFU
Type
Supply
Supply
Supply
–
Description
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.
The command interface is disabled when VCC ≤ VLKO. This prevents WRITE operations from ac-
cidentally damaging the data during power-up, power-down, and power surges. If the pro-
gram/erase controller is programming or erasing during this time, then the operation aborts,
and the contents being altered will be invalid.
A 0.1μF capacitor should be connected between VCC and VSS to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required
during PROGRAM and ERASE operations. (See DC Characteristics.)
I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be
powered independently from VCC.
Ground: All VSS pins must be connected to the system ground.
Reserved for future use: RFUs should be not connected.
Memory Organization
Memory Configuration
The main memory array is divided into 128KB or 64KW uniform blocks.
Memory Map – 256Mb Density
Table 3: 256Mb, Blocks[255:0]
Block
255
⋮
127
⋮
63
⋮
0
Block
Size
128KB
Address Range (x8)
Start
End
1FE 0000h
1FF FFFFh
⋮
0FE 0000h
⋮
0FF FFFFh
⋮
07E 0000h
⋮
07F FFFFh
⋮
000 0000h
⋮
001 FFFFh
Block
Size
64KW
Address Range (x16)
Start
End
0FF 0000h
0FF FFFFh
⋮
07F 0000h
⋮
07F FFFFh
⋮
03F 0000h
⋮
03F FFFFh
⋮
000 0000h
⋮
000 FFFFh
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet M29W256GL.PDF ] |
Número de pieza | Descripción | Fabricantes |
M29W256GH | Parallel NOR Flash Embedded Memory | Micron Technology |
M29W256GL | Parallel NOR Flash Embedded Memory | Micron Technology |
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