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PDF IDT5P49EE601 Data sheet ( Hoja de datos )

Número de pieza IDT5P49EE601
Descripción LOW POWER CLOCK GENERATOR
Fabricantes Integrated Device Technology 
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PRELIMINARY DATASHEET
VERSACLOCK® LOW POWER CLOCK GENERATOR
IDT5P49EE601
Description
The IDT5P49EE601 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to six differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional
32.768kHz crystal oscillator is available to provide a real
time clock or non-critical performance MHz processor
clock.
The IDT5P49EE601 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise.
There are total six 8-bit output dividers. One output bank
can be configured to support LVTTL or LVDS. All other
outputs are always set to LVTTL. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I2C EEPROM master interface
FAST (400kHz) mode I2C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– Outputs - 1 pair selectable 3.3V LVDS
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
1.8V VDD Core Voltage
Available in 24pin 4x4mm QFN packages
-40 to +85 C Industrial Temp operation
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
1
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IDT5P49EE601 pdf
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
PLL Features and Descriptions
8-bit
D
VCO
1-bit 11-bit
AM
PLL Block Diagram
PLLA
Ref-Divider
(D) Values
1 - 255
Feedback
Pre-Divider
(XDIV)
Values
1 or 41
Feedback Programmable Spread Spectrum
(M) Values Loop Bandwidth Generation Capability
6 - 2047
Yes
No
PLLB
1 - 255
4 6 - 2047
Yes
Yes
PLLC
PLLD
1 - 255
1 - 255
1 or 8 bit
divide2
1 or 41
6 - 2047
6 - 2047
Yes
Yes
No
No
1.XDIVA or XDIVD=0, A=1. XDIVA or XDIVD=1, A=4.
2.XDIVC =0, A=1. XDIVC=1 turns on 8 bit predivide multiplier, A=FBC2[7:0]. Total feedback divide equals
FBC[10:0] *FBC2[7:0].
Crystal Input (XIN/REF)
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50maximum equivalent series resonance.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The crystal cpacitors are internal to the device and have an
effective value of 8pF.
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
( )FOUT = FIN *
A*M
D
ODIV
(Eq. 2)
Where FIN is the reference frequency, A is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and FOUT is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
5
IDT5P49EE601 REV C 061110

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IDT5P49EE601 arduino
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
Progsave
Progread Command Frame
Note:
PROGWRITE is for writing to the IDT5P49EE601 registers.
PROGREAD is for reading the IDT5P49EE601 registers.
PROGSAVE is for saving all the contents of the
IDT5P49EE601 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM
contents to the IDT5P49EE601 registers.
Progrestore
During PROGRESTORE, outputs will be turned off to
ensure that no improper voltage levels are experienced
before initialization.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
11
IDT5P49EE601 REV C 061110

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