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PDF KSZ9031RNX Data sheet ( Hoja de datos )
| Número de pieza | KSZ9031RNX | |
| Descripción | Gigabit Ethernet Transceiver | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ9031RNX
Gigabit Ethernet Transceiver
with RGMII Support
Revision 2.2
General Description
The KSZ9031RNX is a completely integrated triple-speed
(10Base-T/100Base-TX/1000Base-T) Ethernet physical-
layer transceiver for transmission and reception of data on
standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9031RNX provides the reduced gigabit media
independent interface (RGMII) for direct connection to
RGMII MACs in gigabit Ethernet processors and switches
for data transfer at 10/100/1000Mbps.
The KSZ9031RNX reduces board cost and simplifies
board layout by using on-chip termination resistors for the
four differential pairs and by integrating an LDO controller
to drive a low-cost MOSFET to supply the 1.2V core.
The KSZ9031RNX offers diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9031 I/Os and the
board. The LinkMD® TDR-based cable diagnostic identifies
faulty copper cabling. Remote and local loopback functions
verify analog and digital data paths.
The standard KSZ9031RNX is available in the 48-pin,
lead-free QFN package, and the AEC-Q100 automotive
qualified parts, KSZ9031RNXUA and KSZ9031RNXVA,
are available in the 48-pin lead-free WQFN package (see
Ordering Information).
Data sheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Features
• Single-chip 10/100/1000Mbps IEEE 802.3-compliant
Ethernet transceiver
• RGMII timing supports on-chip delay according to
RGMII Version 2.0, with programming options for
external delay and making adjustments and corrections
to TX and RX timing paths
• RGMII with 3.3V/2.5V/1.8V tolerant I/Os
• Auto-negotiation to automatically select the highest link-
up speed (10/100/1000Mbps) and duplex (half/full)
• On-chip termination resistors for the differential pairs
• On-chip LDO controller to support single 3.3V supply
operation – requires only one external FET to generate
1.2V for the core
• Jumbo frame support up to 16KB
• 125MHz reference clock output
• Energy detect power-down mode for reduced power
consumption when the cable is not attached
• Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode and clock stoppage for 100Base-TX/
1000Base-T and transmit amplitude reduction with
10Base-Te option
• Wake-On-LAN (WOL) support with robust custom-
packet detection
• AEC-Q100 qualified for automotive applications
(KSZ9031RNXUA, KSZ9031RNXVA)
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 14, 2015
Revision 2.2
1 page  
Micrel, Inc.
KSZ9031RNX
Loopback Mode..................................................................................................................................................................... 30
Local (Digital) Loopback ...................................................................................................................................................................... 30
Remote (Analog) Loopback................................................................................................................................................................. 31
LinkMD® Cable Diagnostic .................................................................................................................................................... 32
NAND Tree Support .............................................................................................................................................................. 32
Power Management .............................................................................................................................................................. 33
Energy-Detect Power-Down Mode ...................................................................................................................................................... 33
Software Power-Down Mode ............................................................................................................................................................... 33
Chip Power-Down Mode...................................................................................................................................................................... 33
Energy Efficient Ethernet (EEE)............................................................................................................................................ 34
Transmit Direction Control (MAC-to-PHY) ........................................................................................................................................... 35
Receive Direction Control (PHY-to-MAC) ............................................................................................................................................ 36
Registers Associated with EEE ........................................................................................................................................................... 37
Wake-On-LAN ....................................................................................................................................................................... 38
Magic-Packet Detection....................................................................................................................................................................... 38
Customized-Packet Detection ............................................................................................................................................................. 38
Link Status Change Detection ............................................................................................................................................................. 39
Typical Current/Power Consumption .................................................................................................................................... 40
Register Map ......................................................................................................................................................................... 42
IEEE-Defined Registers....................................................................................................................................................................... 42
Vendor-Specific Registers ................................................................................................................................................................... 42
Standard Registers ............................................................................................................................................................... 44
MMD Registers...................................................................................................................................................................... 54
MMD Registers – Descriptions ............................................................................................................................................................ 55
Absolute Maximum Ratings .................................................................................................................................................. 65
Operating Ratings ................................................................................................................................................................. 65
Electrical Characteristics....................................................................................................................................................... 65
Timing Diagrams ................................................................................................................................................................... 69
RGMII Timing ...................................................................................................................................................................................... 69
Auto-Negotiation Timing ...................................................................................................................................................................... 72
MDC/MDIO Timing .............................................................................................................................................................................. 73
Power-Up/Power-Down/Reset Timing ................................................................................................................................................. 74
Reset Circuit.......................................................................................................................................................................... 75
Reference Circuits – LED Strap-In Pins................................................................................................................................ 76
Reference Clock – Connection and Selection ...................................................................................................................... 77
On-chip LDO Controller – MOSFET Selection...................................................................................................................... 77
Magnetic – Connection and Selection .................................................................................................................................. 78
Package Information and Recommended Land Pattern ....................................................................................................... 80
May 14, 2015
5 Revision 2.2
5 Page 
Micrel, Inc.
KSZ9031RNX
Pin Description (Continued)
Pin Number
Pin Name
Type(2)
16
DVDDH
P
Pin Function
3.3V, 2.5V, or 1.8V digital VDD_I/O
LED1 output: Programmable LED1 output
Config mode:
The voltage on this pin is sampled and latched during the power-
up/reset process to determine the value of PHYAD[0]. See the
Strapping Options section for details.
PME_N output:
Programmable PME_N output (pin option 1). This pin function
requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a
range from 1.0kΩ to 4.7kΩ. When asserted low, this pin
signals that a WOL event has occurred.
This pin is not an open-drain for all operating modes.
The LED1 pin is programmed by the LED_MODE strapping option (Pin 41), and is
defined as follows.
Single-LED Mode
LED1/
Activity
Pin State LED Definition
PHYAD0/
No activity
H OFF
17 I/O Activity (RX, TX) Toggle Blinking
PME_N1
Tri-Color Dual-LED Mode
Link/Activity
Link off
1000 Link / No activity
1000 Link / Activity (RX, TX)
100 Link / No activity
100 Link / Activity (RX, TX)
10 Link / No activity
10 Link / Activity (RX, TX)
Pin State
LED2 LED1
HH
LH
Toggle H
HL
H Toggle
LL
Toggle Toggle
LED Definition
LED2 LED1
OFF OFF
ON OFF
Blinking OFF
OFF ON
OFF Blinking
ON ON
Blinking Blinking
For tri-color dual-LED mode, LED1 works in conjunction with LED2 (Pin 15) to
indicate 10Mbps link and activity.
18
DVDDL
P 1.2V digital VDD
19
TXD0
I RGMII mode: RGMII TD0 (Transmit Data 0) input
20
TXD1
I RGMII mode: RGMII TD1 (Transmit Data 1) input
21
TXD2
I RGMII mode: RGMII TD2 (Transmit Data 2) input
22
TXD3
I RGMII mode: RGMII TD3 (Transmit Data 3) input
23
DVDDL
P 1.2V digital VDD
24
GTX_CLK
I RGMII mode:RGMII TXC (Transmit Reference Clock) input
25
TX_EN
I RGMII mode:RGMII TX_CTL (Transmit Control) input
26
DVDDL
P 1.2V digital VDD
RXD3/
RGMII mode: RGMII RD3 (Receive Data 3) output
27
MODE3
I/O Config mode: The pull-up/pull-down value is latched as MODE3 during power-
up/reset. See the Strapping Options section for details.
RXD2/
RGMII mode: RGMII RD2 (Receive Data 2) output
28
MODE2
I/O Config mode: The pull-up/pull-down value is latched as MODE2 during power-
up/reset. See the Strapping Options section for details.
May 14, 2015
11 Revision 2.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ9031RNX.PDF ] | |
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