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PDF HCPL-2202 Data sheet ( Hoja de datos )

Número de pieza HCPL-2202
Descripción Very High CMR/ Wide VCC Logic Gate Optocouplers
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! HCPL-2202 Hoja de datos, Descripción, Manual

Very High CMR, Wide VCC Logic
Gate Optocouplers
Technical Data
HCPL-2201
HCPL-2211
HCPL-2231
HCPL-0201
HCNW2201
HCPL-2202
HCPL-2212
HCPL-2232
HCPL-0211
HCNW2211
Features
• 10 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1000 V
(HCPL-2211/2212/0211/
2232, HCNW2211)
• Wide Operating VCC Range:
4.5 to 20 Volts
• 300 ns Propagation Delay
Guaranteed over the Full
Temperature Range
• 5 Mbd Typical Signal Rate
• Low Input Current (1.6 mA
to 1.8 mA)
• Hysteresis
• Totem Pole Output (No
Pullup Resistor Required)
• Available in 8-Pin DIP,
SOIC-8, Widebody Packages
• Guaranteed Performance
from -40°C to 85°C
• Safety Approval
UL Recognized -2500 V rms
for 1 minute (5000 V rms
for 1 minute for
HCNW22XX) per UL1577
CSA Approved
VDE 0884 Approved with
VIORM = 630 V peak (HCPL-
2211/2212 Option 060 only)
and VIORM = 1414 V peak
(HCNW22XX only)
• MIL-STD-1772 Version
Available
(HCPL-52XX/62XX)
Applications
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
• Ground Loop Elimination
• Pulse Transformer
Replacement
• High Speed Line Receiver
• Power Control Systems
Description
The HCPL-22XX, HCPL-02XX,
and HCNW22XX are optically-
coupled logic gates. The
HCPL-22XX, and HCPL-02XX
contain a GaAsP LED while the
HCNW22XX contains an AlGaAs
LED. The detectors have totem
pole output stages and optical
receiver input stages with built-in
Schmitt triggers to provide logic-
compatible waveforms, eliminat-
ing the need for additional
waveshaping.
A superior internal shield on the
HCPL-2211/12, HCPL-0211,
Functional Diagram
HCPL-2201/11
HCPL-0201/11
HCNW2201/11
NC 1
8 VCC
HCPL-2202/12
NC 1
8 VCC
ANODE 2
7 VO
ANODE 2
7 NC
CATHODE 3
6 NC CATHODE 3
6 VO
NC 4
SHIELD
5 GND
NC 4
SHIELD
5 GND
HCPL-2231/32
ANODE 1 1
8 VCC
CATHODE 1 2
7 VO1
CATHODE 2 3
6 VO2
TRUTH TABLE
(POSITIVE LOGIC)
LED
VO
ON
OFF
HIGH
LOW
ANODE 2 4
SHIELD
5 GND
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.

1 page




HCPL-2202 pdf
5
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW2201/11)
11.15 ± 0.15
(0.442 ± 0.006)
87 6 5
1234
PAD LOCATION (FOR REFERENCE ONLY)
9.00 ± 0.15
(0.354 ± 0.006)
(06.2.1452)TYP.
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
(04..10508)MAX.
1.3
(0.051)
0.9
(0.035)
12.30 ± 0.30
(0.484 ± 0.012)
11.00 MAX.
(0.433)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
1.00 ± 0.15
(0.039 ± 0.006)
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
7° NOM.
Solder Reflow Temperature Profile (HCPL-02XX and Gull Wing Surface Mount Option 300 Parts)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
0
T = 115°C, 0.3°C/SEC
T = 100°C, 1.5°C/SEC
1 23 4 5 6 7 8
TIME – MINUTES
T = 145°C, 1°C/SEC
9 10 11 12
Note: Use of nonchlorine activated fluxes is highly recommended.

5 Page





HCPL-2202 arduino
11
Package Characteristics
Parameter
Sym. Min. Typ. Max. Units
Test Conditions
Fig. Note
Input-Output Momentary
Withstand HCNW22XX
Voltage*
VISO 2500
5000
V rms RH < 50%, t = 1 min.
TA = 25°C
5, 10
5, 11
Input-Output Resistance
RI-O
1012
VI-O = 500 Vdc
HCNW22XX
1012 1013
TA = 25°C
1011
TA = 100°C
Input-Output Capacitance CI-O
HCNW22XX
0.6 pF
f = 1 MHz,
0.5 0.6
TA = 25°C VI-O = 0 Vdc
Input-Input Insulation
Leakage Current
II-I
0.005
µA Relative Humidity = 45%,
t = 5 s, VI-I = 500 V
Resistance (Input-Input)
RI-I
1011
VI-I = 500 V
Capacitance (Input-Input) CI-I
0.25 pF f = 1 MHz
5
5
12
12
12
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,”
publication number 5963-2203E.
Notes:
1. Each channel.
2. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
3. Duration of output short circuit time should not exceed 10 ms.
4. For single devices, input capacitance is measured between pin 2 and pin 3.
5. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
6. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the
leading edge of the output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input
pulse to the 1.3 V point on the trailing edge of the output pulse.
7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state,
VO > 2.0 V. CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic
low state, VO < 0.8 V.
8. For HCPL-2202/12, VO is on pin 6.
9. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.
10. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for one second
(leakage detection current limit, II-O 5 µA). This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 V rms for one second
(leakage detection current limit, II-O 5 µA). This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table.
12. For HCPL-2231/32 only. Measured between pins 1 and 2, shorted together, and pins 3 and 4, shorted together.

11 Page







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