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PDF AT25DF641A-MH-Y Data sheet ( Hoja de datos )

Número de pieza AT25DF641A-MH-Y
Descripción 2.7V Minimum SPI Serial Flash Memory
Fabricantes Adesto 
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AT25DF641A
64-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual–I/O Support
Features
DATASHEET
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidSoperation
Supports Dual-Input Program and Dual-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output time (tV) of 5ns maximum
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
128 Sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte One-Time Programmable (OTP) Security Register
64 bytes factory preprogrammed
64 bytes user programmable
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast program and erase times
2.5ms typical Page Program (256 bytes) time
75ms typical 4KB Block Erase time
300ms typical 32KB Block Erase time
600ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
25mA Active Read current (typical at 20MHz)
5μA Deep Power-Down current (typical)
Endurance: 100,000 program/erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (0.208” wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
8793D–DFLASH–5/2013

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AT25DF641A-MH-Y pdf
3. Block Diagram
Figure 3-1. Block Diagram
Control and
CS Protection Logic
SCK
SI (SIO)
SO (SOI)
WP
HOLD
Interface
Control
and
Logic
Y-Decoder
X-Decoder
Note:
SIO and SOI pin naming convention is used for Dual-I/O commands.
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
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AT25DF641A-MH-Y arduino
7.2 Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO. To
perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode of 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is always output
on the SO pin. During the first clock cycle, bit 7 of the first data byte is output on the SO pin, while bit 6 of the same data
byte is output on the SIO pin. During the next clock cycle, bits 5 and 4 of the first data byte are output on the SO and SIO
pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the
last byte (7FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The
CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4. Dual-Output Read Array
CS
SCK
SIO
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Opcode
Address Bits A23-A0
Dummy Byte
Output
Output
Data Byte 1 Data Byte 2
00 111011AAAAAA
MSB
MSB
A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4
MSB
High-impedance
D7 D5 D3 D1 D7 D5 D3 D1 D7 D5
MSB
MSB
MSB
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
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