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PDF NCV7428D15R2G Data sheet ( Hoja de datos )

Número de pieza NCV7428D15R2G
Descripción System Basis Chip
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NCV7428
System Basis Chip with
Integrated LIN and Voltage
Regulator
Description
NCV7428 is a System Basis Chip (SBC) integrating functions
typically found in automotive Electronic Control Units (ECUs).
NCV7428 provides and monitors the low−voltage power supply for
the application microcontroller and other loads and includes a LIN
transceiver.
Features
Control Logic
Ensures safe power−up sequence and the correct reaction to
different supply conditions
Controls mode transitions including the power management and
bus wakeup treatment
Generates reset
3.3 V or 5 V VOUT Supply depending on the Version from a
Low−drop Voltage Regulator
Can deliver up to 70 mA with accuracy of ±2%
Supplies typically the ECU’s microcontroller
Undervoltage detector with a reset output to the supplied
microcontroller
LIN Transceiver
LIN2.x and J2602 compliant
TxD dominant timeout protection
Transceiver mode controlled by dedicated input pin
Protection and Monitoring Functions
Thermal shutdown protection
Load dump protection (45 V)
LIN Bus pin protected against transients in an automotive
environment
ESD protection level for LIN and VS > ±8 kV
These are Pb−Free Devices
Quality
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Typical Applications
Automotive
Industrial Networks
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751AZ
MARKING DIAGRAM
8
NV7428xx
ALYW G
G
1
NV7428−5 = NCV7428D15
NV7428−3 = NCV7428D13
NV7428L5 = NCV7428D1L5
NV7428L3 = NCV7428D1L3
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
1
VS
2
EN
3
GND
4
LIN
8
VOUT
7
RSTN
6
TxD
5
RxD
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 1
1
Publication Order Number:
NCV7428/D

1 page




NCV7428D15R2G pdf
NCV7428
Definitions
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 4, unless stated
otherwise. All voltages are referenced to GND (Pin 3). Positive currents flow into the respective pin.
Table 6. DC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise
specified. Typical values are given at VS = 12 V and TJ = 25°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min Typ Max Unit
SUPPLY MONITORING
VS_PORH
VS threshold for the power−up
of the circuit
VS rising
3.3 4 V
VS_PORL
VS threshold for the Shutdown
of the circuit
VS falling
2.2 3 V
VOUT_RES_5
VOUT monitoring threshold
NV7428−5
VOUT falling
4.55 4.75 V
VOUT_RES_3
VOUT monitoring threshold
NV7428−3
VOUT falling
2.97
3.135
V
VOUT_RES_hys5
VOUT monitoring threshold
hysteresis for 5 V versions
0.1 V
VOUT_RES_hys33 VOUT monitoring threshold
hysteresis for 3.3 V versions
0.06 V
CURRENT CONSUMPTION
IVS_LIN_Active_rec
IVS_LIN_Wakeup
VS supply current
VS supply current (Note 6)
LIN Active, LIN bus recessive
Standby mode; LIN Wakeup,
LIN bus recessive; IVOUT = 0 mA
VS = 13.5 V, TJ < 105°C
1.8 mA
25 40 mA
IVS_Sleep
VS supply current (Note 6)
Sleep mode; LIN Wakeup, LIN bus
recessive; VOUT off, VOUT < 0.5 V
VS = 13.5 V, TJ < 105°C
12 25 mA
VOUT REGULATOR
VOUT_5
VOUT regulator output voltage
NCV7428−5
VOUT regulator active,
0 < IVOUT < 70 mA, Static
regulation, VS = 5.5 V to 28 V
4.9 5 5.1 V
VOUT_3
VOUT regulator output voltage
NCV7428−3
VOUT regulator active,
0 < IVOUT < 70 mA, Static
regulation, VS = 4.5 V to 28 V
3.234 3.3 3.366 V
ILIM_VOUT
VOUT current limitation
VOUT regulator active;
current flowing to VOUT load
70 120 350 mA
VDROP_VOUT
Drop−out voltage between VS
and VOUT
5.5 V < VS < 40 V;
IVOUT = 70 mA
0.55 V
ISINK_VOUT
VOUT sink current
VOUT regulator active, current
flowing into the VOUT pin
100 240 400 mA
CVOUT
VOUT regulator filtering
capacitance (Note 5)
Equivalent series resistance < 7 W
1.8
10
mF
LIN TRANSMITTER
VLIN_dom_LoSup LIN dominant output voltage
TxD = Low; VS = 7.3 V
1.2 V
VLIN_dom_HiSup LIN dominant output voltage
TxD = Low; VS = 18 V
2.0 V
VLIN_REC
LIN recessive output voltage
TxD = High; ILIN = 10 mA (Note 4) VS – 1.5
VS V
ILIN_lim
Short circuit current limitation
VLIN = VS = 18 V
40 200 mA
Rslave
Internal Pull−up Resistance
LIN Normal or Receive−only mode
20
33
47 kW
CLIN
Capacitance on pin LIN (Note 6)
20 30 pF
4. The voltage drop in Normal mode between LIN and VS pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
5. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
6. Values based on design and characterization. Not tested in production.
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NCV7428D15R2G arduino
NCV7428
Shutdown Mode
The Shutdown mode is a passive state, in which all
NCV7428 resources are inactive. The Shutdown mode
provides a defined starting point for the circuit in case of
supply undervoltage, thermal Shutdown or the first supply
connection.
On−chip power−supply VOUT is switched off and the LIN
pin remains passive so that it does not disturb the
communication of other nodes connected to the LIN bus.
RxD pin stays pulled to VOUT. No wakeups can be detected.
RSTN pin is forced Low – RSTN Low level is guaranteed
for VS supply above VS_DigOut_Low.
The Shutdown mode is entered asynchronously whenever
the VS level falls below the power−on−reset level VS_PORL.
The Shutdown mode is left only when the VS supply
exceeds the high power−on−reset level VS_PORH while
junction temperature is below TJ_SD. When exiting the
Shutdown mode, NCV7428 always enters the Reset mode.
RESET Mode
The Reset mode is a transient mode providing a defined
RSTN pulse for the application microcontroller.
VOUT supply is kept active. The LIN pin is passive so that
it does not disturb the communication of other nodes
connected to the bus. RxD pin is High if no wakeup was
detected, RxD Low level indicates pending LIN wakeup.
Pin RSTN is forced Low.
Reset mode will be entered as a consequence of one of the
following events:
Shutdown mode is exited
Thermal Shutdown mode is exited
VOUT voltage falls below VOUT_RES level
LIN wakeup or EN = High was detected in Sleep mode
Normally, the Reset mode is left when VOUT voltage is
above VOUT_RES threshold and defined time treset elapses.
The RSTN pin is internally released to High and the chip
then goes to the Normal or Standby mode, depending on EN
state.
Normal Mode
Normal mode is entered from Standby mode after a host
request – driving EN pin High (Figure 9), or if EN pin is
High when leaving Reset mode – treset time elapsed
(Figure 8).
LIN transceiver is in Active mode. VOUT is kept on. Pin
RSTN remains High.
Standby Mode
Standby mode is entered from Normal mode after host
request – EN pin falling edge followed by TxD pin High.
TxD is sampled tsynch + tmodesel after EN edge (Figure 9).
Standby mode is also entered if EN pin is Low when leaving
Reset mode – treset time elapsed (Figure 7).
LIN transceiver is in Wakeup mode – RxD pin is latched
Low after valid Wakeup recognition until Normal mode is
requested. VOUT is kept active. Pin RSTN remains High.
Sleep Mode
Sleep mode can be only entered from Normal mode after
a host request – EN pin falling edge followed by TxD pin
Low. TxD is sampled tsynch + tmodesel after EN pin edge
(Figure 10).
VOUT regulator is switched off, LIN transceiver is in the
Wakeup mode.
If LIN wakeup is detected or EN goes High, Reset mode
is entered. LIN wakeup is signaled by RxD, which remains
Low until Normal mode is restored (EN is High).
Thermal Shutdown
The device junction temperature is monitored in order to
avoid permanent degradation or damage of the chip.
Junction temperature exceeding the Shutdown level TJ_SD
puts the chip into Thermal Shutdown mode.
In Thermal Shutdown mode, VOUT regulator is switched
off. LIN transceiver is in Wakeup mode and can detect bus
Wakeup. RxD pin stays pulled to VOUT or is driven Low
after valid Wakeup recognition. RSTN pin is pulled low. The
mode is automatically left only when the junction cools
down below the TJ_SD threshold.
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