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PDF AR9344 Data sheet ( Hoja de datos )

Número de pieza AR9344
Descripción Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4/5 GHz Premium SoC
Fabricantes Atheros　
Logotipo Atheros Logotipo

AR9344 image


1. 802.11n 2x2 2.4/5 GHz SoC






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Data Sheet
PRELIMINARY
December 2010
AR9344 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2
2.4/5 GHz Premium SoC for Advanced WLAN Platforms
General Description
The Atheros AR9344 is a highly integrated and
feature-rich IEEE 802.11n 2x2 2.4/5 GHz System-
on-a-Chip (SoC) for advanced WLAN platforms.
It includes a MIPS 74Kc processor, PCI Express
1.1 Root Complex and Endpoint interfaces, five
port IEEE 802.3 Fast Ethernet Switch with MAC/
PHY, one MII/RMII/RGMII interface, one USB
2.0 MAC/PHY, and external memory interface
for serial Flash, SDRAM, DDR1 or DDR2, I2S/
SPDIF-Out audio interface, SLIC VOIP/PCM
interface, two UARTs, and GPIOs that can be
used for LED controls or other general purpose
interface configurations.
The AR9344 supports 802.11n operations up to
144 Mbps for 20 MHz and 300 Mbps for 40 MHz
respectively, and 802.11a/b/g data rates.
Additional features include Maximal Likelihood
(ML) decoding, Low-Density Parity Check
(LDPC), Maximal Ratio Combining (MRC), Tx
Beamforming (TxBF), and On-Chip One-Time
Programmable (OTP) memory.
The AR9344 PCIE Root Complex interface can be
used to connect to another Atheros single-chip
MAC/BB/radio for dual concurrent WLAN
applications. The AR9344 supports booting from
either NOR or NAND flash. If NOR flash is used
as boot codestore, an additional NAND flash
device can still be connected, for end-user multi-
media storage and other applications.
When connecting the AR9344 to an external host
through the PCIE Endpoint interface, or the USB
Device interface, the AR9344 can off load the host
CPU from computation- intensive functions,
allowing it to focus on its dedicated tasks.
AR9344 System Block Diagram
Features
■ 74Kc MIPS processor with 64 KB I-Cache and
32 KB D-Cache, operating at up to 533 MHz
■ External 16- or 32-bit DDR1, DDR2 operating
at up to 200 MHz (400 M transfers/sec), or 16-
bit SDRAM memory interface operating at up
to 200 MHz
■ NAND and SPI NOR Flash memory support
■ 10/100 Ethernet Switch with five IEEE 802.3
Ethernet LAN ports
■ MII/RMII/RGMII interface
■ 802.3az Energy Efficient Ethernet compliant
■ Hardware-based NAT & ACL accelerators for
Ethernet interface
■ Both PCI Express 1.1 Root Complex and
Endpoint interfaces supported
simultaneously
■ One USB 2.0 controller with built-in MAC/
PHY supports Host or Device mode
■ Boot from external CPU via PCIE, USB, xMII,
eliminating need for external flash
■ I2S/SPDIF-out audio interface
■ SLIC for VOIP/PCM
■ One low-speed UART (115 Kbps), one high-
speed UART (3 Mbps), and multiple GPIO
pins for general purpose I/O
■ Fully integrated RF Front-End including PAs
and LNAs
■ Optional external LNA/PA
■ 25 MHz or 40 MHz reference clock input
■ 1.2 V switching regulator
■ Advanced power management with dynamic
clock switching for ultra-low power modes
■ 409-pin BGA package
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, Ethos®, IQUE®,
No New Wires®, Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total
802.11®, U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain
Technology™, Install N Go™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros
logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1

1 page




AR9344 pdf
PRELIMINARY
8.1.10 DQS Delay Tap Control for Byte 2
(TAP_CONTROL_2) ................ 119
8.1.11 DQS Delay Tap Control for Byte 3
(TAP_CONTROL_3) ................ 120
8.1.12 GMAC0 Interface Write Buffer
Flush
(DDR_WB_FLUSH_GMAC0) . 120
8.1.13 GMAC1 Interface Write Buffer
Flush
(DDR_WB_FLUSH_GMAC1) . 120
8.1.14 USB Interface Write Buffer Flush
(DDR_WB_FLUSH_USB) ........ 120
8.1.15 PCIE Interface Write Buffer Flush
(DDR_WB_FLUSH_PCIE) ....... 121
8.1.16 WMAC Interface Write Buffer Flush
(DDR_WB_FLUSH_WMAC) .. 121
8.1.17 SRC1 Interface Write Buffer Flush
(DDR_WB_FLUSH_SRC1) ...... 121
8.1.18 SRC2 Interface Write Buffer Flush
(DDR_WB_FLUSH_SRC2) ...... 121
8.1.19 DDR2 Configuration
(DDR_DDR2_CONFIG) ........... 122
8.1.20 DDR EMR2 (DDR_EMR2) ....... 122
8.1.21 DDR EMR3 (DDR_EMR3) ....... 122
8.1.22 AHB Master Timeout Control
(AHB_MASTER_TIMEOUT_MAX)
..................................................... 122
8.1.23 AHB Timeout Current Count
(AHB_MASTER_TIMEOUT_CUR
NT) .............................................. 123
8.1.24 Timeout Slave Address
(AHB_MASTER_TIMEOUT_SLV_
ADDR) ........................................ 123
8.1.25 DDR Controller Configuration
(DDR_CTL_CONFIG) .............. 123
8.1.26 DDR Self Refresh Control ..............
(DDR_SF_CTL) ......................... 124
8.1.27 Self Refresh Timer (SF_TIMER) 124
8.1.28 WMAC Flush (WMAC_FLUSH) ..
124
8.2 UART0 (Low-Speed) Registers .......... 125
8.2.1 Receive Buffer (RBR) ................ 125
8.2.2 Transmit Holding (THR) ......... 125
8.2.3 Divisor Latch Low (DLL) ........ 126
8.2.4 Divisor Latch High (DLH) ...... 126
8.2.5 Interrupt Enable (IER) .............. 126
8.2.6 Interrupt Identity (IIR) ............. 127
8.2.7 FIFO Control (FCR) .................. 127
8.2.8 Line Control (LCR) ................... 128
8.2.9 Modem Control (MCR) ........... 128
8.2.10 Line Status (LSR) ...................... 129
8.2.11 Modem Status (MSR) ............... 129
8.3 GPIO Registers ..................................... 130
8.3.1 GPIO Output Enable (GPIO_OE) .
131
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
GPIO Input Value (GPIO_IN) 131
GPIO Output Value (GPIO_OUT)
131
GPIO Per Bit Set (GPIO_SET) . 131
GPIO Per Bit Clear (GPIO_CLEAR)
132
GPIO Interrupt Enable (GPIO_INT)
132
GPIO Interrupt Type
(GPIO_INT_TYPE) ................... 132
GPIO Interrupt Polarity
(GPIO_INT_POLARITY) ......... 132
GPIO Interrupt Pending
(GPIO_INT_PENDING) .......... 133
8.3.10 GPIO Interrupt Mask
(GPIO_INT_MASK) ................. 133
8.3.11 GPIO Ethernet LED Routing Select
(GPIO_IN_ETH_SWITCH_LED) .
133
8.3.12 GPIO Function 0
(GPIO_OUT_FUNCTION0) .... 134
8.3.13 GPIO Function 1
(GPIO_OUT_FUNCTION1) .... 134
8.3.14 GPIO Function 2
(GPIO_OUT_FUNCTION2) .... 135
8.3.15 GPIO Function 3
(GPIO_OUT_FUNCTION3) .... 135
8.3.16 GPIO Function 4
(GPIO_OUT_FUNCTION4) .... 135
8.3.17 GPIO In Signals 0
(GPIO_IN_ENABLE0) ............. 136
8.3.18 GPIO In Signals 1
(GPIO_IN_ENABLE1) ............. 136
8.3.19 GPIO In Signals 2
(GPIO_IN_ENABLE2) ............. 136
8.3.20 GPIO In Signals 3
(GPIO_IN_ENABLE3) ............. 136
8.3.21 GPIO In Signals 4
(GPIO_IN_ENABLE4) ............. 137
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC • 5
December 2010 • 5

5 Page





AR9344 arduino
PRELIMINARY
8.12.13 PCIE MSI Lower Address
(PCIE_MSI_ADDR) .................. 215
8.12.14 PCIE MSI Data Value
(PCIE_MSI_DATA) .................. 215
8.12.15 PCIE Interrupt Status
(PCIE_INT_STATUS) ............... 216
8.12.16 PCIE Interrupt Mask
(PCIE_INT_MASK) .................. 217
8.13 WDMA Registers ................................ 218
8.13.1 Command (CR) ......................... 219
8.13.2 Configuration and Status (CFG) ...
219
8.13.3 Rx DMA Data Buffer Pointer
Threshold (RXBUFPTR_THRESH)
220
8.13.4 Tx DMA Descriptor Pointer
Threshold (TXDPPTR_THRESH) .
220
8.13.5 Maximum Interrupt Rate Threshold
(MIRT) ........................................ 220
8.13.6 Interrupt Global Enable (IER) . 221
8.13.7 Tx Interrupt Mitigation Thresholds
(TIMT) ........................................ 221
8.13.8 Rx Interrupt Mitigation Thresholds
(RIMT) ........................................ 221
8.13.9 Tx Configuration (TXCFG) ...... 222
8.13.10 Rx Configuration (RXCFG) ... 222
8.13.11 MIB Control (MIBC) ............... 223
8.13.12 Global Tx Timeout (GTT) ...... 223
8.13.13 Global Tx Timeout Mode (GTTM)
223
8.13.14 Carrier Sense Timeout (CST) . 224
8.13.15 Size of High and Low Priority
(RXDP_SIZE) ............................. 224
8.13.16 MAC Rx High Priority Queue
RXDP Pointer
(RX_QUEUE_HP_RXDP) ........ 224
8.13.17 MAC Rx Low Priority Queue
RXDP Pointer
(RX_QUEUE_LP_RXDP) ......... 224
8.13.18 Primary Interrupt Status (ISR_P)
225
8.13.19 Secondary Interrupt Status 0
(ISR_S0) ...................................... 226
8.13.20 Secondary Interrupt Status 1
(ISR_S1) ...................................... 226
8.13.21 Secondary Interrupt Status 2
(ISR_S2) ...................................... 227
8.13.22 Secondary Interrupt Status 3
(ISR_S3) ...................................... 228
8.13.23 Secondary Interrupt Status 4
(ISR_S4) ...................................... 228
8.13.24 Secondary Interrupt Status 5
(ISR_S5) ...................................... 228
8.13.25 Primary Interrupt Mask (IMR_P)
229
8.13.26 Secondary Interrupt Mask 0
(IMR_S0) .................................... 230
8.13.27 Secondary Interrupt Mask 1
(IMR_S1) .................................... 230
8.13.28 Secondary Interrupt Mask 2
(IMR_S2) .................................... 231
8.13.29 Secondary Interrupt Mask 3
(IMR_S3) .................................... 231
8.13.30 Secondary Interrupt Mask 4
(IMR_S4) .................................... 232
8.13.31 Secondary Interrupt Mask 5
(IMR_S5) .................................... 232
8.13.32 Primary Interrupt Status Read and
Clear (ISR_P_RAC) ................... 232
8.13.33 Secondary Interrupt Status 0
(ISR_S0_S) .................................. 233
8.13.34 Secondary Interrupt Status 1
(ISR_S1_S) .................................. 233
8.13.35 Secondary Interrupt Status 2
(ISR_S2_S) .................................. 233
8.13.36 Secondary Interrupt Status 3
(ISR_S3_S) .................................. 233
8.13.37 Secondary Interrupt Status 4
(ISR_S4_S) .................................. 233
8.13.38 Secondary Interrupt Status 5
(ISR_S5_S) .................................. 233
8.14 WQCU Registers ................................. 234
8.14.1 Tx Queue Descriptor (Q_TXDP) ..
234
8.14.2
QCU_STATUS_RING_START_AD
DRESS Lower 32 bits of Address
(Q_STATUS_RING_START) ... 235
8.14.3
QCU_STATUS_RING_END_ADD
R Lower 32 Bits of Address
(Q_STATUS_RING_END) ...... 235
8.14.4 QCU_STATUS_RING_CURRENT
Address
(Q_STATUS_RING_CURRENT) ..
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC • 11
December 2010 • 11

11 Page







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