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PDF PALCE22V10H-15 Data sheet ( Hoja de datos )

Número de pieza PALCE22V10H-15
Descripción 24-Pin EE CMOS Versatile PAL Device
Fabricantes AMD 
Logotipo AMD Logotipo



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No Preview Available ! PALCE22V10H-15 Hoja de datos, Descripción, Manual

FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/20/25
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s As fast as 5-ns propagation delay and
142.8 MHz fMAX (external)
s Low-power EE CMOS
s 10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s Varied product term distribution allows up to
16 product terms per output for complex
functions
s Peripheral Component Interconnect (PCI)
compliant (-5/-7/-10)
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic
for replacing conventional SSI/MSI gates and flip-flops
at a reduced chip count.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
BLOCK DIAGRAM
CLK/I0
1
s Global asynchronous reset and synchronous
preset for initialization
s Power-up reset for initialization and register
preload for testability
s Extensive third-party software and programmer
support through FusionPLD partners
s 24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flat-
pack and 28-pin PLCC and LCC packages save
space
s 5-ns and 7.5-ns versions utilize split lead-
frames for improved performance
high or active low. The output configuration is
determined by two bits controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PALCE22V10 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
I1 - I11
11
8 10
Programmable
AND Array
(44 x 132)
12 14 16 16 14 12 10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5
Publication# 16564 Rev. D Amendment /0
Issue Date: February 1996
I/O6 I/O7 I/O8
I/O9 16564D-1
2-217

1 page




PALCE22V10H-15 pdf
Registered Output Configuration
Each macrocell of the PALCE22V10 includes a D-type
flip-flop for data storage and synchronization. The flip-
flop is loaded on the LOW-to-HIGH transition of the
clock input. In the registered configuration (S1 = 0), the
array feedback is from Q of the flip-flop.
AMD
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(S1 = 1). In the combinatorial configuration the feedback
is from the pin.
AR
DQ
CLK Q
SP
S0 = 0
S1 = 0
S0 = 0
S1 = 1
Registered/Active Low
AR
S0 = 1
S1 = 0
DQ
CLK Q
SP
Combinatorial/Active Low
S0 = 1
S1 = 1
Registered/Active High
Combinatorial/Active High
16564D-5
Figure 2. Macrocell Configuration Options
PALCE22V10 Family
2-221

5 Page





PALCE22V10H-15 arduino
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0 V
VOUT = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
Typ Unit
5
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
tPD
tS1
tS2
tH
tCO
tSKEWR
tAR
tARW
tARR
tSPR
tWL
tWH
fMAX
tEA
tER
Parameter Description
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback
Setup Time from SP to Clock
Hold Time
Clock to Output
Skew Between Registered Outputs (Note 3)
Asynchronous Reset to Registered Output
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Synchronous Preset Recovery Time
Clock Width
LOW
HIGH
Maximum
Frequency
(Note 4)
External Feedback
Internal Feedback (fCNT)
No Feedback
1/(tS + tCO)
1/(tS + tCF) (Note 5)
1/(tWH + tWL)
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
-7
PDIP
PLCC
Min Max Min Max
3 7.5 3 7.5
5 4.5
66
00
2 5 2 4.5
11
10 10
77
77
77
3.5 3.0
3.5 3.0
100 111
125 133
142.8
166
7.5 7.5
7.5 7.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Skew is measured with all outputs switching in the same direction.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE22V10H-7 (Com’l)
2-227

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