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PDF CY7C4281V Data sheet ( Hoja de datos )

Número de pieza CY7C4281V
Descripción Low-Voltage Deep Sync FIFOs
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY7C4261V
CY7C4281V/CY7C4291V
16K/64K/128K × 9
Low-Voltage Deep Sync™ FIFOs
16K/64K/128K × 9 Low-Voltage Deep Sync™ FIFOs
Features
3.3 V operation for low-power consumption and easy
integration into low-voltage systems
High-speed, low-power, first-in first-out (FIFO) memories
16K × 9 (CY7C4261V)
64K × 9 (CY7C4281V)
128K × 9 (CY7C4291V)
0.35-micron CMOS for optimum speed or power
High-speed 100-MHz operation (10-ns read/write cycle times)
Low power
ICC = 25 mA
ISB = 4 mA
Fully asynchronous and simultaneous read and write operation
Empty, full, and programmable Almost Empty and Almost Full
status flags
Output-enable (OE) pin
Independent read- and write-enable pins
Supports free-running 50% duty cycle clock inputs
Width-expansion capability
Pin-compatible 3.3 V solutions for CY7C4261/81/91
Pin-compatible density upgrade within the CY7C42X1V family
Pb-free packages available
Functional Description
The CY7C4261/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine bits
wide. The CY7C4261/81/91V are pin-compatible with the lower
densities in the CY7C42x1V Synchronous FIFO family.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
Selection Guide
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1
and WEN2/LD are held active, data is continually written into the
FIFO on each WCLK cycle. The output port is controlled in a
similar manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the
CY7C4261/81/91V has an output-enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run
independently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion is
possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow of
data.
The CY7C4261/81/91V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to single
word granularity. The programmable flags default to Empty +7
and Full –7.
The flags are synchronous, that is, they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full, and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using an advanced 0.35 μ
CMOS technology. Input ESD protection is greater than 2001 V,
and latch-up is prevented by the use of guard rings.
For a complete list of related documentation, click here.
Description
Maximum frequency
Maximum access time
Minimum cycle time
Minimum data or enable setup
Minimum data or enable hold
Maximum flag delay
Active power supply current (ICC1)
Commercial
7C4261/81V-10
100
8
10
3.5
0
8
25
7C4261/91V-15
66.7
10
15
4
0
10
25
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4261V
16K × 9
32-pin PLCC
CY7C4281V
64K × 9
32-pin PLCC
CY7C4291V
128K × 9
32-pin PLCC
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06013 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2016

1 page




CY7C4281V pdf
CY7C4261V
CY7C4281V/CY7C4291V
Architecture
The CY7C4261/81/91V consists of an array of 16K, 64K, or 128K
words of nine bits each (implemented by a dual-port array of
SRAM cells), a read pointer, a write pointer, control signals
(RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF,
PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q0–8) go LOW tRSF after the
rising edge of RS. In order for the FIFO to reset to its default
state, the user must not read or write while RS is LOW. All flags
are guaranteed to be valid tRSF after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D0–8 pins is written
into the FIFO on each rising edge of the WCLK signal. Similarly,
when the REN1 and REN2 signals are active LOW and EF is
active HIGH, data in the FIFO memory will be presented on the
Q0-8 outputs. New data will be presented on each rising edge of
RCLK while REN1 and REN2 are active. REN1 and REN2 must
set up tENS before RCLK for it to be a valid read function. WEN1
and WEN2 must occur tENS before WCLK for it to be a valid write
function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register will be available to the Q0-8 outputs after
tOE. If devices are cascaded, the OE function will only output
data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0-8 outputs even
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS
= LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 9-bit offset registers
contained in the CY7C4261/81/91V for writing or reading data to
these registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again. Figure 2 shows the registers sizes and default
values for the various device types.
Figure 2. Offset Register Location and Default Values
16k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
85
0
(MSB)
Default Value = 000h
87
Full Offset (LSB) Reg
Default Value = 007h
0
85
0
(MSB)
Default Value = 000h
87
64k x 9
0
Empty Offset (LSB) Reg.
Default Value = 007h
128k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
87
(MSB)
Default Value = 000h
87
Full Offset (LSB) Reg
Default Value = 007h
87
(MSB)
Default Value = 000h
0
0
0
8
(MSB)
Default Value = 000h
87
Full Offset (LSB) Reg
Default Value = 007h
8
(MSB)
Default Value = 000h
0
0
0
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
Document Number: 38-06013 Rev. *K
Page 5 of 22

5 Page





CY7C4281V arduino
CY7C4261V
CY7C4281V/CY7C4291V
Switching Waveforms
WCLK
D0 –D17
WEN1
tCLKH
Figure 6. Write Cycle Timing
tCLK
tCLKL
tDS tDH
tENS
tENH
WEN2
(if applicable)
FF
RCLK
tWFF
tSKEW1 [12]
tWFF
No Operation
No Operation
REN1, REN2
RCLK
REN1, REN2
tENS
EF
Q0 –Q17
OE
WCLK
tOLZ
tCLKH
Figure 7. Read Cycle Timing
tCKL
tCLKL
tENH
tREF
tA
NO OPERATION
tOE
tSKEW1[13]
tREF
Valid Data
tOHZ
WEN1
WEN2
Notes
12.
tbSeKtEwWe1enistthheermisiinnigmeudmgetimofeRbCeLtwKeaenndathriesinrigsinRgCeLdKgeedogfeWaCndLKa
rising WCLK edge to guarantee that FF will go HIGH during
is less than tSKEW1, then FF may not change state until the
the current
next WCLK
clock cycle. If
rising edge.
the
time
13.
tbSeKtEwWe1enistthheermisiinnigmeudmgetimofeWbCetLwKeeannda
rising WCLK edge and a rising
the rising edge of RCLK is less
RCLK edge to guarantee that EF will go HIGH during
than tSKEW2, then EF may not change state until the
the current
next RCLK
clock
rising
cycle.
edge.
It
the
time
Document Number: 38-06013 Rev. *K
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