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PDF FT2232H Data sheet ( Hoja de datos )
| Número de pieza | FT2232H | |
| Descripción | Dual High Speed USB to Multipurpose UART/FIFO IC | |
| Fabricantes | FTDI | |
| Logotipo |  |
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Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
Future Technology
Devices International Ltd
FT2232H Dual High Speed
USB to Multipurpose
UART/FIFO IC
The FT2232H is FTDI‟s 5th generation of USB
devices. The FT2232H is a USB 2.0 High
Speed (480Mb/s) to UART/FIFO IC. It has the
capability of being configured in a variety of
industry standard serial or parallel interfaces.
The FT2232H has the following advanced
features:
Single chip USB to dual serial / parallel ports
with a variety of configurations.
Entire USB protocol handled on the chip. No
USB specific firmware programming required.
USB 2.0 High Speed (480Mbits/Second) and
Full Speed (12Mbits/Second) compatible.
Dual Multi-Protocol Synchronous Serial Engine
(MPSSE) to simplify synchronous serial protocol
(USB to JTAG, I2C, SPI or bit-bang) design.
Dual independent UART or FIFO or MPSSE
ports.
Independent Baud rate generators.
RS232/RS422/RS485 UART Transfer Data Rate
up to 12Mbaud. (RS232 Data Rate limited by
external level shifter).
USB to parallel FIFO transfer data rate up to 8
Mbyte/Sec.
Single channel synchronous FIFO mode for
transfers upto 40 Mbytes/Sec
CPU-style FIFO interface mode simplifies CPU
interface design.
MCU host bus emulation mode configuration
option.
Fast Opto-Isolated serial interface option.
FTDI‟s royalty-free Virtual Com Port (VCP) and
Direct (D2XX) drivers eliminate the
requirement for USB driver development in
most cases.
Adjustable receive buffer timeout.
Option for transmit and receive LED drive
signals on each channel.
Enhanced bit-bang Mode interface option with
RD# and WR# strobes
FT245B-style FIFO interface option with bi-
directional data bus and simple 4 wire
handshake interface.
Highly integrated design includes +1.8V LDO
regulator for VCORE, integrated POR function
and on chip clock multiplier PLL (12MHz –
480MHz).
Asynchronous serial UART interface option with
full hardware handshaking and modem
interface signals.
Fully assisted hardware or X-On / X-Off
software handshaking.
UART Interface supports 7/8 bit data, 1/2 stop
bits, and Odd/Even/Mark/Space/No Parity.
Auto-transmit enable control for RS485 serial
applications using TXDEN pin.
Operational configuration mode and USB
Description strings configurable in external
EEPROM over the USB interface.
Configurable I/O drive strength (4, 8, 12 or
16mA) and slew rate.
Low operating and USB suspend current.
Supports bus powered, self powered and high-
power bus powered USB configurations.
UHCI/OHCI/EHCI host controller compatible.
USB Bulk data transfer mode (512 byte packets
in High Speed mode).
+1.8V (chip core) and +3.3V I/O interfacing
(+5V Tolerant).
Extended -40°C to 85°C industrial operating
temperature range.
Compact 64-LD Lead Free LQFP or QFN
package
+3.3V single supply operating voltage range.
ESD protection for FT2232H IO‟s:
Human Body Model (HBM) ±2kV,
Machine Mode (MM) ±200V,
Charge Device Model (CDM) ±500V,
Latch-up free.
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or
electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as
to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages
Copyright © 2012 Future Technology Devices International Limited
1
1 page  
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
2 FT2232H Block Diagram
VCC 3V3 IN
V1.8OUT
1.8 Volt
LDO
Regulator
EECS
EESK
EEDATA
OSCI
OSCO
USBDP
USBDM
RREF
EEPROM
Interface
UTMI PHY
USB Protocol Engine
And FIFO Control
RESET#
TEST
RESET
Generator
120 MHz
Bau1d2R0aMteHz
Generator
Dual Port TX
Buffer
4K Bytes
Dual Port RX
Buffer
4K Bytes
120 MHz
Bau1d2R0aMteHz
Generator
Dual Port TX
Buffer
4K Bytes
Dual Port RX
Buffer
4K Bytes
Figure 2.1 FT2232H Block Diagram
For a description of each function please refer to Section 4.
MPSSE/
Multi-
purpose
UART/FIFO
Controller
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
PWREN#
SUSPEND#
MPSSE/
Multi-
purpose
UART/FIFO
Controller
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
PWRSAV# /
BCBUS7
Copyright © 2012 Future Technology Devices International Limited
5
5 Page 
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
Pin No.
Name
Type
Description
2
OSCI
INPUT Oscillator input.
3
OSCO
OUTPUT Oscillator output.
6 REF INPUT Current reference – connect via a 12KΩ resistor @ 1% to GND.
7 DM INPUT USB Data Signal Minus.
8 INPUT USB Data Signal Plus.
DP
13
TEST
INPUT IC test pin – for normal operation should be connected to GND.
14
RESET#
INPUT
60
PWREN#
OUTPUT
36 SUSPEND# OUTPUT
59
PWRSAV#
INPUT
Table 3.2 Common Function pins
Reset input (active low).
Active low power-enable output.
PWREN# = 0: Normal operation.
PWREN# =1 : USB SUSPEND mode or device has not been configured.
This can be used by external circuitry to power down logic when device
is in USB suspend or has not been configured.
Active low when USB is in suspend mode.
USB Power Save input. This is an EEPROM configurable option used
when the FT2232H is used in a self powered mode and is used to
prevent forcing current down the USB lines when the host or hub is
powered off.
PWRSAV# = 1 : Normal Operation
PWRSAV# = 0 : FT2232H forced into SUSPEND mode.
PWRSAV# can be connected to GND (via a 10KΩ resistor) and another
resistor (e.g. 4K7) connected to the VBUS of the USB connector. When
this input goes high, then it indicates to the FT2232H that it is
connected to a host PC. When the host or hub is powered down then
the FT2232H is held in SUSPEND mode.
Pin No. Name
Type
Description
EECS
I/O EEPROM – Chip Select. Tri-State during device reset.
63
EECLK
OUTPUT Clock signal to EEPROM. Tri-State during device reset. When not in reset, this
62 outputs the EEPROM clock.
EEDATA
I/O EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to Data-Out
61 of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via
a 10K resistor for correct operation. Tri-State during device reset.
Table 3.3 EEPROM Interface Group
Copyright © 2012 Future Technology Devices International Limited
11
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| Páginas | Total 67 Páginas | |
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