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PDF SAA16M16 Data sheet ( Hoja de datos )

Número de pieza SAA16M16
Descripción DDR2 SDRAM
Fabricantes SpecTek 
Logotipo SpecTek Logotipo



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®
DDR2 SDRAM
256Mb: x4, x8, x16
DDR2 SDRAM
SAA64M4.....– 16 Meg x 4 x 4
SAA32M8.....– 8 Meg x 8 x 4
SAA16M16.....– 4 Meg x 16 x 4
For the latest data sheet, please refer to the SpecTek Web
site: http://www.spectek.com
Features
• ROHS compliant
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Programmable CAS Latency (CL): 3 and 4
• Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
Options1, 2
• SpecTek Memory
• Configuration
64 Meg x 4 (16 Meg x 4 x 4)
32 Meg x 8 ( 8 Meg x 8 x 4)
16 Meg x 16 (4 Meg x 16 x 4)
• Product Code
DDR2
• Density
256 Megabits
• Voltage/Refresh
1.8V/8K refresh
• Package – Lead-Free
x4, x8
60-ball FBGA (8mm x 12mm)
x16
84-ball FBGA (8mm x 14mm)
• Package – Leaded
x4, x8
60-ball FBGA (8mm x 12mm)
x16
84-ball FBGA (8mm x 14mm)
• Timing – Cycle Time
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Designation
SAA
64M4
32M8
16M16
Ux3
6x3
O8
FIF
FPF
FIL
FPL
-3
-37E
NOTE: 1. See page 42 for part number options and desig-
nations used prior to March 2005.
2. See page 42 for part number options and desig-
nations used prior to July 2006.
3. Contact SpecTek Sales for details on availability
of the "x" placeholders
Architecture 64 Meg x 4 32 Meg x 8 16 Meg x 16
Configuration 16 Meg x 4 x 4
Refresh Count
8K
Row Addressing 8K (A0–A12)
Bank Addressing 4 (BA0–BA1)
Column
Addressing
2K (A0–A9, A11)
8 Meg x 8 x 4 4 Meg x 16 x 4
8K 8K
8K (A0–A12) 8K (A0–A12)
4 (BA0–BA1) 4 (BA0–BA1)
1K (A0–A9) 512 (A0–A8)
Table 1: Key Timing Parameters
Speed
Grade
-3
-37E
Data Rate (MHz)
CL = 4
NA
533
CL = 5
667
533
tRCD
(ns)
15
15
tRP
(ns)
15
15
tRc
(ns)
60
60
Part Number Example:
SAA32M8U26AO8FIF-37E
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256Mb_1.fm - Rev. C 7/06 EN
1 SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

1 page




SAA16M16 pdf
® 256Mb: x4, x8, x16
DDR2 SDRAM
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part marking that is differ-
ent from the part number. SpecTek’s new FBGA part
marking decoder makes it easier to understand FBGA
part marking. Visit the SpecTek web site at www.spec-
tek.com/pdfs/fbga_decoder.pdf .
General Description
The 256Mb DDR2 SDRAM is a high-speed, CMOS
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM. The functional block diagrams of the 16
Meg x 16, 32 Meg x 8, and 64 Meg x 4 devices, respec-
tively are shown in the Functional Description section.
Ball assignments for the 64 Meg x 4 are shown in
Figure 1 and signal descriptions are shown in Table 1.
Ball assignments for the 32 Meg x 8 and 64 Meg x 4 are
shown in Figure 2 and signal descriptions are shown in
Table 2.
The 256Mb DDR2 SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 256Mb DDR2
SDRAM effectively consists of a single 4n-bit-wide,
one-clock-cycle data transfer at the internal DRAM
core and four corresponding n-bit-wide, one-half-
clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmit-
ted externally, along with data, for use in data capture
at the receiver. DQS is a strobe transmitted by the
DDR2 SDRAM during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs.
The x16 offering has two data strobes, one for the
lower byte (LDQS, LDQS#) and one for the upper byte
(UDQS, UDQS#).
The 256Mb DDR2 SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR2 SDRAM are
burst-oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight
with another read, or a burst write of eight with
another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.
As with standard DDR SDRAMs, the pipelined,
multibank architecture of DDR2 SDRAMs allows for
concurrent operation, thereby providing high, effec-
tive bandwidth by hiding row precharge and activation
time.
A self refresh mode is provided, along with a power-
saving power-down mode.
All inputs are compatible with the JEDEC standard
for SSTL_18. All full drive-strength outputs are
SSTL_18-compatible.
NOTE: 1. The functionality and the timing specifica-
tions discussed in this data sheet are for the
DLL-enabled mode of operation.
2. Throughout the data sheet, the various fig-
ures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ
collectively, unless specifically stated other-
wise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
3. Complete functionality is described
throughout the document and any page or
diagram may have been simplified to con-
vey a topic and may not be inclusive of all
requirements.
4. Any specific requirement takes precedence
over a general statement.
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256Mb_2.fm - Rev. C 7/06 EN
5 SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

5 Page





SAA16M16 arduino
® 256Mb: x4, x8, x16
DDR2 SDRAM
Figure 4: Functional Block Diagram (32 Meg x 8)
ODT
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
CONTROL
LOGIC
MODE REGISTERS
15
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
REFRESH 13
COUNTER
13
ROW-
ADDRESS
MUX
13
BANK3
BANK2
BANK1
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8,192
BANK3
BANK2
BANK1
BANK0
MEMORY
ARRAY
(8,192 x 256 x 32)
SENSE AMPLIFIERS
8,192
2
BANK
CONTROL
2 LOGIC
COLUMN-
8
10 ADDRESS
COUNTER/
LATCH
2
I/O GATING
DM MASK LOGIC
256
(x32)
COLUMN
DECODER
COL0,COL1
8
32 8
READ
LATCH
8
8
MUX
8
DATA
CK,CK#
DLL
DRVRS
DQS
GENERATOR
2
DQS, DQS#
INPUT
REGISTERS
11
32
11
41
WRITE
FIFO
1
MASK
&
DRIVERS
32
1
1
1
RCVRS
internal
CK, CK#
CK OUT
8
8
32
8
8
8
CK IN
8
DATA
8
88
COL0,COL1
2
Figure 5: Functional Block Diagram (16 Meg x 16)
ODT CONTROL VDDQ
sw1 sw2
sw1 sw2
R1 R2
R1 R2
sw1 sw2
R1 R2
R1 R2
sw1 sw2
R1 R2
R1 R2
VssQ
DQ0–DQ7
DQS, DQS#
RDQS#
RDQS
DM
ODT
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
CONTROL
LOGIC
MODE REGISTERS
15
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
REFRESH 13
COUNTER
13
ROW-
ADDRESS
MUX
13
BANK3
BANK2
BANK1
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8,192
BANK3
BANK2
BANK1
BANK0
MEMORY
ARRAY
(8,192 x 128 x 64)
SENSE AMPLIFIERS
8,192
2
BANK
2
CONTROL
LOGIC
COLUMN-
7
9 ADDRESS
COUNTER/
LATCH
2
I/O GATING
DM MASK LOGIC
128
(x64)
COLUMN
DECODER
COL0,COL1
16
64 READ 16
LATCH 16
16
MUX
16
DATA
CK,CK#
DLL
DRVRS
DQS
GENERATOR
4
UDQS, UDQS#
LDQS, LDQS#
INPUT
REGISTERS
22
64
22
82
WRITE
FIFO
2
MASK
&
64 DRIVERS
2
2
2
RCVRS
Internal
CK, CK#
CK OUT
16
16
64
16
16
16
CK IN
DATA 16
16
16 16
COL0,COL1
4
ODT CONTROL VDDQ
sw1 sw2
sw1 sw2
R1 R2
R1 R2
sw1 sw2
R1 R2
R1 R2
sw1 sw2
R1 R2
R1 R2
VssQ
DQ0–DQ15
UDQS, UDQS#
LDQS, LDQS#
UDM, LDM
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256Mb_2.fm - Rev. C 7/06 EN
11
SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

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