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PDF NCP5222 Data sheet ( Hoja de datos )
| Número de pieza | NCP5222 | |
| Descripción | High Performance Dual-Channel / Two-Phase Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5222
High Performance
Dual-Channel / Two-Phase
Synchronous Buck
Controller for Notebook
Power System
The NCP5222, a fast−transient−response and high−efficiency
dual−channel / two−phase buck controller with built−in gate drivers,
provides multifunctional power solutions for notebook power system.
180° interleaved operation between the two channels / phases has a
capability of reducing cost of the common input capacitors and
improving noise immunity. The interleaved operation also can reduce
cost of the output capacitors with the two−phase configuration. Input
supply voltage feedforward control is employed to deal with wide
input voltage range. On−line programmable and automatic
power−saving control ensures high efficiency over entire load range.
Fast transient response reduces requirement on the output filters. In the
dual−channel operation mode, the two output power rails are regulated
individually. In the two−phase operation mode, the two output power
rails are connected together by an external switch and current−sharing
control is enabled to balance power delivery between phases.
Features
• Wide Input Voltage Range: 4.5 V to 27 V
• Adjustable Output Voltage Range: 0.8 V to 3.3 V
• Option for Dual−Channel and Two−Phase Modes
• Fixed Nominal Switching Frequency: 300 kHz
• 180° Interleaved Operation Between the Two Channels in
Continue−Conduction−Mode (CCM)
• Adaptive Power Control
• Input Supply Voltage Feedforward Control
• Transient−Response−Enhancement (TRE) Control
• Resistive or Inductor’s DCR Current Sensing
• 0.8% Internal 0.8 V Reference
• Internal 1 ms Soft−Start
• Output Discharge Operation
• Built−in Adaptive Gate Drivers
• Input Supplies Undervoltage Lockout (UVLO)
• Output Overvoltage and Undervoltage Protections
• Accurate Over Current Protection
• Thermal Shutdown Protection
• QFN−28 Package
• This is a Pb−Free Device
Typical Applications
• CPU Chipsets Power Supplies
• Notebook Applications
http://onsemi.com
MARKING
DIAGRAM
1
QFN28
CASE 485AR
N5222
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
7654321
8 CS2−/
Vo2
9 CS2+
10 EN2/
SKIP2
11 BST2
12 DH2
13 SWN2
14 DL2
NCP5222
AGND
29
CS1−/
Vo1
28
CS1+ 27
EN1/ 26
S KIP1
BST1 25
DH1 24
SWN1 23
DL1 22
15 16 17 18 19 20 21
(Top View)
ORDERING INFORMATION
Device
NCP5222MNR2G
Package
QFN28
(Pb−Free)
Shipping†
4000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
February, 2010 − Rev. 0
1
Publication Order Number:
NCP5222/D
1 page  
NCP5222
PIN DESCRIPTION
Pin
No. Symbol
Descriptions
1
ICS1
Current−Sense Output 1. Output of the current−sense amplifier of channel 1.
2 FB1 Feedback 1. Output voltage feedback of channel 1.
3 COMP1 COMP1. Output of the error amplifier of channel 1.
4 VIN Vin. Input supply voltage monitor input.
5 COMP2 COMP2. Output of the error amplifier of channel 2.
6 FB2 Feedback 2. Output voltage feedback of channel 2.
7
ICS2
Current−Sense Output 2. Output of the current−sense amplifier of channel 2.
8
CS2−/
Current Sense 2−. Inductor current differential sense inverting input of Channel 2. Output Voltage 2. Connection
Vo2 to output of Channel 2.
9
CS2+
Current Sense 2+. Inductor current differential sense non−inverting input of Channel 2.
10
EN2 /
Enable 2. Enable logic input of Channel 2. Skip 2. Power−saving operation (FPWM and Skip) programming pin
Skip2
of Channel 2.
11
BST2
BOOTSTRAP Connection 2.Channel 2 high−side gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
12
DH2
High−Side Gate Drive 2. Gate driver output of the high−side N−Channel MOSFET for channel 2.
13
SWN2
Switch Node 2. Switch node between the high−side MOSFET and low−side MOSFET of Channel 2.
14 DL2 Low−Side Gate Drive 2. Gate driver output of the low−side N−Channel MOSFET for channel 2.
15 PGND2 Power Ground 2. Ground reference and high−current return path for the low−side gate driver of channel 2.
16 PGOOD2 Power GOOD 2. Power good indicator of the output voltage of channel 2. (Open drained)
17
VCC
VCC. This pin powers the control section of IC.
18 DRVS / Gate Driver for Switch. Gate driver output for the external switch in dual−phase configuration. Dual−Channel.
2CH
Dual−channel configuration programming pin.
19
VCCP
VCC Power. This pin powers internal gate drivers.
20 PGOOD1 Power GOOD 1. Power good indicator of the output voltage of channel 1. (Open drained)
21 PGND1 Power Ground 1. Ground reference and high−current return path for the low−side gate driver of channel 1.
22 DL1 Low−Side Gate Drive 1. Gate driver output of the low−side N−Channel MOSFET for channel 1.
23
SWN1
Switch Node 1. Switch node between the high−side MOSFET and low−side MOSFET of Channel 1.
24
DH1
High−Side Gate Drive 1. Gate driver output of the high−side N−Channel MOSFET for channel 1.
25
BST1
BOOTSTRAP Connection 1. Channel 1 high−side gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
26
EN1 /
Enable 1. Enable logic input of Channel 1. Skip 1. Power−saving operation (FPWM and Skip) programming pin
Skip1
of Channel 1.
27
CS1+
Current Sense 1+. Inductor current differential sense non−inverting input of Channel 1.
28
CS1−/
Current Sense 1−. Inductor current differential sense inverting input of Channel 1. Output Voltage 1. Connection
Vo1 to output of Channel 1.
29
AGND
Analog Ground. Low noise ground for control section of IC.
http://onsemi.com
5
5 Page 
VIN
VCC
EN1
EN2
DRVS
PGOOD1
PGOOD2
Vo1
Vo2
3 .6V
4.2 5V
NCP5222
3.5us
53us
0 .5V
150us
67us
1ms 260 us
0.2V
150us
57us
1ms 260us
Mode detection Ch2 r amping up
complete.
complet e.
PGOOD2
vali d.
Ch1 sof tst art
begins.
Ch1 i n
regul ation.
DRVS soft start
complet e.
EN2 goes high and
mode detection starts.
System and Ch2 reset complete
and Ch2 soft start begins.
Ch2 i n EN1 goes hi gh
regul ati on. and Ch1 reset.
Ch1 rampi ng up
complet e.
PGOOD1 valid and Ch1 power down.
DRVS soft start begins.
Figure 6. Timing Diagram in Two−Phase Mode
Ch2 power down.
Control Logic
The NCP5222 monitors VCC with undervoltage lockout
(UVLO) function. If VCC is in normal operation range, the
converter has a soft−start after EN signal goes high. The
internal digital soft−start time is fixed to 1 ms. The two
channels share one DAC ramping−up circuit. If the two ENs
become high at the same time (within 5 ms), the two channels
start soft−start together; If one channel’s EN comes when the
other channel is powering up, the channel starts powering up
after the other channel completes soft start. If one channel’s
EN comes when the other channel is in any fault condition,
the channel does not start powering up until the fault is
cleared. The NCP5222 has output discharge operation
through one internal 20 W MOSFET per channel connected
from CS−/Vo pin to PGND pin, when EN is low or the
channel is under any fault condition.
Current−Sense Network
In the NCP5222, the output current of each channel is
sensed differentially. A high gain and low offset−voltage
differential amplifier in each channel allows low−resistance
current−sense resistor or low−DCR inductor to be used to
minimize power dissipation. For lossless inductor current
sensing as shown in Figure 7, the sensing RC network
should satisfy:
L
DCR
+
RCS1 @ RCS2
RCS1 ) RCS2
@
CCS
+
kCS
@
RCS1
@
CCS
(eq.
1)
where the dividing−down ratio kCS is
kCS
+
RCS2
RCS1 ) RCS2
(eq. 2)
DCR is a DC resistance of an inductor, and normally CCS
is selected to be around 0.1 mF. The current−sense input
voltage across CS+ and CS− is
VCS + kCS @ IL @ DCR
(eq. 3)
If there is a need to compensate measurement error caused
by temperature, an additional resistance network including
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11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NCP5222.PDF ] | |
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