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PDF AN-6961 Data sheet ( Hoja de datos )

Número de pieza AN-6961
Descripción Critical Conduction Mode PFC Controller
Fabricantes Fairchild Semiconductor 
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AN-6961
Critical Conduction Mode PFC Controller
Description
This application note describes a power factor correction
(PFC) circuit using the FAN6961. Both the features of this
controller, as well as the operation of the power factor
correction circuit, are presented in detail. Based on the
proposed design guideline, a design example with detailed
parameters demonstrates the performance of the controller.
Introduction
The FAN6961 PFC controller is an 8-pin Boundary Current
Mode (BCM) IC intended for controlling PFC pre-regulators.
The FAN6961 provides a controlled on-time to regulate the
output DC voltage and achieve natural power factor
correction. The maximum on-time of the switch is
programmable to ensure safe operation during AC
brownouts. An innovative multi-vector error amplifier is built
in to provide rapid transient response and precise output
voltage clamping. Once the output feedback loop is opened,
the output driver (GD) is disabled to provide protection of
the system. The start-up current is lower than 20µA and the
operating current has been reduced to 5mA. The supply
voltage can be operated up to 25V, maximizing application
flexibility. The FAN6961 also enables cycle-by-cycle current
limiting protection for the external power MOSFET.
Figure 1. Power Factor Correction Circuit
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 4/8/09
www.fairchildsemi.com

1 page




AN-6961 pdf
AN-6961
VZCD
10V
2.1V
1.75V
VDS
VO
t
Vg(t)
2Vg(t) - VO
Gate t
Figure 14.
Inhibit time
t
VDS & VZCD & Gate Waveform
Maximum On-Time Operation
The on-time of the power MOSFET is varied with the output
power and the AC input voltage. While the AC input voltage
decreases, the on-time increases accordingly. The
maximum on-time limit ton,max can be programmed by the
resistor connected between MOT and GND pin.
ton,max
= Rmot (kΩ)
25
24
(µs)
(4)
The range of the maximum on-time is designed to be within
10~50μs; 25μs is recommended.
VCC Over-Voltage Protection
A VCC over-voltage protection avoids damage when the
voltage VDD exceeds the internal threshold due to an open-
loop failure. Once the protection is triggered, the PWM
output is turned off.
Peak Current Limiting
The switch current is sensed across a resistor and supplied
to an input terminal of a comparator. A voltage higher than
the 0.82V threshold voltage on the CS pin immediately
terminates the current switching cycle, activating cycle-by-
cycle current limiting.
Leading-Edge Blanking (LEB)
A turn-on spike inevitably occurs at the CS pin when the
power MOSFET is switched on. At the beginning of each
switching pulse, the current-limit comparator is disabled for
around 350ns to avoid premature termination. The gate drive
output cannot be switched off during the blanking period.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off threshold voltages are fixed
internally at 12V and 9.5V, respectively. This hysteresis
behavior guarantees a one-shot start-up, as long as a
proper start-up resistor and hold-up capacitor are used.
APPLICATION NOTE
Output Driver
With a low on resistance and a high current driving
capability, the output driver can drive an external capacitive
load larger than 3000pF. Cross conduction currents are
avoided to minimize heat dissipation, improving efficiency
and reliability. This output driver is internally clamped by a
17V Zener diode.
Lab Note
Before rework or solder/desolder on the power supply,
discharge the primary capacitors by external bleeding
resistor. Otherwise, the PWM IC may be destroyed by
external high voltage during solder/desolder.
Design Guideline
PFC Inductor Design
As shown in Figure 15, considering one AC line voltage
cycle, the minimum switching frequency fs,min occurs at the
peak of the AC line voltage. To avoid audible noise, the
minimum switching frequency fs,min must be above audible
frequency. The appropriate inductance can be calculated by
Equation 5. The minimum switching frequency fs,min may
happen in AC maximum or minimum input voltage,
depending on the output voltage. Therefore, calculate both
the maximum and the minimum input voltages, then choose
the lower inductance value.
( )Lb
=
η Vpk2
4 Po
Vo Vpk
Vo fs.min
where:
Lb is the PFC inductor,
η is conversion efficiency,
Vpk is the peak of the AC line voltage,
PO is rated output power,
VO is PFC output voltage,
fs,min is the minimum switching frequency.
(5)
Switching Frequency
Line input voltage[Vin(t)*200]
7.00E+04
6.00E+04
5.00E+04
4.00E+04
3.00E+04
2.00E+04
1.00E+04
0.00E+00
0
10
Figure 15.
20 30 40 50 60 70 80
Time(S/5000)
Frequency vs. Input Voltage
The peak inductor current iLpk can be expressed as:
iL,pk =
4 Po
2 Vrms.min η
(6)
where Vrms.min is the minimum input line rms voltage.
With the internal THD optimization circuit, the real peak
inductor current is smaller than calculated. Usually, the real
peak current is around 95% of calculated value.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 4/8/09
5
www.fairchildsemi.com

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