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PDF 25VF080 Data sheet ( Hoja de datos )

Número de pieza 25VF080
Descripción 8 Mbit SPI Serial Flash
Fabricantes SST 
Logotipo SST Logotipo



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8 Mbit SPI Serial Flash
SST25VF080
FEATURES:
SST25VF0808 Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST25VF080
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 33 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC 200 mil body width
PRODUCT DESCRIPTION
SST’s s erial flash family features a four-wire, SPI-com-
patible interface that allows for a low pin-count package
occupying less board space and ultimately lowering total
system costs. SST25VF080 SPI se rial flash memories
are m anufactured wi th S ST’s pr oprietary, h igh pe rfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reli-
ability a nd manufacturability com pared w ith a lternate
approaches.
The SST 25VF080 de vices significantly im prove p erfor-
mance, w hile lo wering p ower con sumption. T he t otal
energy consumed is a fu nction of th e ap plied voltage,
current, and time of application. Since for any given volt-
age range, the SuperFlash technology uses less current
to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than a lternative f lash m emory technologies. The
SST25VF080 de vices ope rate with a sing le 2.7-3.6V
power supply.
The SST25VF080 devices are offered in an 8-lead SOIC
package with 200 mil body width. See Figure 1 f or pin
assignments.
©2003 Silicon Storage Technology, Inc.
S71250-00-000
10/03
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
http://www.Datasheet4U.com

1 page




25VF080 pdf
8 Mbit SPI Serial Flash
SST25VF080
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low st ate coincides with the f alling ed ge of th e
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next r eaches the active l ow state.
Similarly, if the rising edge of the HOLD# signal does not
Advance Information
coincide wi th th e S CK a ctive low state, then the d evice
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold m ode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with th e device, H OLD# must be dr iven
active high, and CE# must be driven active low. See Figure
17 for Hold timing.
SCK
HOLD#
Active
Hold
FIGURE 3: HOLD CONDITION WAVEFORM
Active
Hold
Active
1250 F03.0
Write Protection
SST25VF080 pr ovides s oftware W rite pr otection. T he
Write Protect pin (WP#) enables or disables the lock-down
function of the st atus r egister. T he Bl ock-Protection bits
(BP1, BP0, and BPL) in the status register provide Write
protection to thememory array and the status register. See
Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is dr iven lo w, the execution of the Wr ite-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-
REGISTER (WRSR) INSTRUCTION
WP#
L1
L0
HX
BPL
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1250
©2003 Silicon Storage Technology, Inc.
5
S71250-00-000
10/03

5 Page





25VF080 arduino
8 Mbit SPI Serial Flash
SST25VF080
Auto Address Increment (AAI) Program
The AAI program instruction alows multiple bytes of data to
be pr ogrammed without r e-issuing t he ne xt s equential
address location. T his f eature de creases total p rogram-
ming ti me when th e e ntire m emory a rray i s to be pro-
grammed. An AA I pr ogram instruction poi nting to a
protected mem ory ar ea wi ll be i gnored. T he s elected
address range must be in the erased state (FFH) when ini-
tiating an AAI program instruction.
Prior t o any w rite op eration, t he Write-Enable (WREN)
instruction must be executed. The AAI program instruction
is initiated by executing an 8-bit command, AFH, followed
by address bits [A23-A0]. Following the addresses, thedata
is input sequentially from MSB (Bit 7) to LSB (Bit 0). CE#
must be driven high before the AAI program instruction is
executed. The user must poll the BUSY bit in the software
Advance Information
status register or wait TBP for the completion of each inter-
nal self-timed Byte-Program cycle. Once the device com-
pletes programming byte, the next sequential address may
be program, enter the8-bit command, AFH, followed by the
data to be programmed. When the last desired byte had
been p rogrammed, e xecute t he W rite-Disable ( WRDI)
instruction, 04H, to terminate AAI. After execution of th e
WRDI command, the user must poll the Status register to
ensure the device completes programming. See Figure 6
for AAI programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected mem ory add ress is r eached, th e
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0).
TBP TBP
CE#
MODE 3 0 1 2 3 4 5 6 7 8
SCK MODE 0
15 16 23 24 31 323 33 43 53 63 73 83 9
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
01
SI
AF
A[23:16] A[15:8] A[7:0]
Data Byte 1
AF Data Byte 2
TBP
CE#
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
01234567
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI AF Last Data Byte
04
05
Write Disable (WRDI) Read Status Register (RDSR)
Instruction to terminate Instruction to verify end of
AAI Operation
AAI Operation
SO DOUT
FIGURE 6: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
1250 F06.0
©2003 Silicon Storage Technology, Inc.
11
S71250-00-000
10/03

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