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PDF OB2278 Datasheet ( Hoja de datos )

Número de pieza OB2278
Descripción Current Mode PWM Controller
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OB2278 datasheet

1 Page

OB2278 pdf
OB2278
Current Mode PWM ControllerLatch Shutdown
ELECTRICAL CHARACTERISTICS
(TA = 25, RI=100K ohm, VDD=16V, if not otherwise noted)
Symbol
Parameter
Test Conditions
Min Typ Max Unit
Supply Voltage (VDD)
I_VDD_Startup VDD Start up Current
VDD =15V Measure
current into VDD
3 20 uA
I_VDD_Ops
UVLO(Enter)
UVLO(Exit)
Operation Current
VDD Under Voltage
Lockout Enter
VDD Under Voltage
Lockout Exit (Startup)
VFB=3V
2.3 mA
8.8 9.8 10.8 V
15.5 16.5 17.5 V
OVP(Latch)
OVP(De-Latch)
VDD Over Voltage Latch
Trigger
VDD Latch Release
Voltage Threshold
26.5 28
7.5
29.5 V
V
I(Vdd)_latch
VDD bleeding current at
latch shutdown when VDD
= 9V
45 uA
TD_OVP
VDD_Clamp
T_Softstart
VDD OVP Debounce time
VDD Zener Clamp Voltage
Soft Start Time
I(VDD ) = 5 mA
80 uSec
35 V
3 mSec
Feedback Input Section(FB Pin)
AVCS
PWM Input Gain
VFB_Open
VFB Open Voltage
ΔVFB /ΔVcs
2.8 V/V
6.2 V
IFB_Short
FB pin short circuit current
Short FB pin to GND,
measure current
0.75
mA
VTH_0D
Zero Duty Cycle FB
Threshold Voltage
0.95 V
VTH_BM
Burst Mode FB Threshold
Voltage
1.6 V
VTH_PL
Power Limiting
Threshold Voltage
FB
4.4 V
TD_PL
Power limiting Debounce
Time
80 mSec
ZFB_IN
Input Impedance
9.0 Kohm
Current Sense Input(Sense Pin)
T_blanking
Sense Input Leading Edge
Blanking Time
300 nSec
ZSENSE_IN
TD_OC
Sense Input Impedance
Over Current Detection
and Control Delay
CL=1nf at GATE,
30 Kohm
70 nSec
Current Limiting Threshold
VTH_OC_0
at No Compensation
I(VIN) = 0uA
0.85 0.90 0.95 V
VTH_OC_1
Oscillator
FOSC
f_Temp
f_VDD
Current Limiting Threshold
at Compensation
I(VIN) = 150uA
Normal
Frequency
Frequency
Stability
Frequency
Stability
Oscillation
Temperature
Voltage
-20to 100
VDD = 12-28V,
0.80 V
60 65 70 KHZ
3%
3%
©On-Bright Electronics
Confidential
-5-
Datasheet
OB_DOC_DS_2278A2

5 Page

OB2278 arduino
OB2278
Current Mode PWM ControllerLatch Shutdown
a photo coupler and affiliated circuits. When OVP
detection signal connected to RT is lower than
VTH_OTP, OB2278 controls system into latch
shutdown. The recovery of the AC/DC system
could only start by resetting internal latch when
VDD voltage drops below VDD_De-latch value.
This could be achieved by unplugging/re-plugging
of AC source in AC start-up configuration.
z Gate Drive
OB2278 Gate is connected to the Gate of an
external MOSFET for power switch control. Too
weak the gate drive strength results in higher
conduction and switch loss of MOSFET while too
strong gate drive output compromises the EMI.
Good tradeoff is achieved through the built-in
totem pole gate drive design with right output
strength and dead time control. The low idle loss
and good EMI system design is easier to achieve
with this dedicated control scheme. An internal
16.5V clamp is added for MOSFET gate
protection at higher than expected VDD input.
z Protection Controls
Good system reliability is achieved with OB2278’s
rich protection features including Cycle-by-Cycle
current limiting (OCP), Over Load Protection (OLP)
with auto-recovery(T version) or latch shutdown(L
version), over temperature protection (OTP) with
latch shutdown, on-chip VDD over voltage
protection (OVP) with latch shutdown and under
voltage lockout (UVLO).
The OCP threshold value is self adjusted lower at
higher current into VIN pin. This OCP threshold
slope adjustment helps to compensate the
increased output power limit at higher AC voltage
caused by inherent Over-Current sensing and
control delay. A constant output power limit is
achieved with recommended OCP compensation
scheme.
At output overload condition, FB voltage is set
higher. When FB input exceeds power limit
threshold value for more than 80mS, control
circuit reacts to turnoff the power MOSFET. This
is so called OLP shutdown. It is either auto-
recovery or latched shutdown depending on
version of OB2278.
Similarly, control circuit shuts down the power
MOSFET when an Over Temperature condition is
detected. This shutdown is latched.
VDD is supplied with transformer auxiliary winding
output. It is clamped when VDD is higher than
35V. MOSFET is shut down when VDD drops
below UVLO(enter) limit and device enters power
on start-up sequence thereafter.
©On-Bright Electronics
Confidential
- 10 -
Datasheet
OB_DOC_DS_2278A2

10 Page





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