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PDF SAM9G45 Data sheet ( Hoja de datos )
| Número de pieza | SAM9G45 | |
| Descripción | AT91SAM ARM-based Embedded MPU | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT91SAM ARM-based Embedded MPU
SAM9G45
DATASHEET
Description
The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user interface function-
ality and high data rate connectivity, including LCD Controller, resistive touch-screen, camera interface, audio,
Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400 MHz and multiple 100+
Mbps data rate peripherals, the SAM9G45 has the performance and bandwidth to the network or local storage
media to provide an adequate user experience.
The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program and data storage. An internal
133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and dis-
tributed memory including a 64-Kbyte SRAM which can be configured as a tightly coupled memory (TCM)
sustains the high bandwidth required by the processor and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and
peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it sup-
ports 0.8 ball pitch package for low cost PCB manufacturing.
The SAM9G45 power management controller features efficient clock gating and a battery backup section min-
imizing power consumption in active and standby modes.
6438K–ATARM–12-Feb-13
http://www.Datasheet4U.com
1 page  
Table 3-1. Signal Description List (Continued)
Signal Name
Function
Type
Active Reference
Level
Voltage Comments
Shutdown, Wakeup Logic
SHDN
Shut-Down Control
Output
VDDBU
Driven at 0V only.
0: The device is in backup
mode
1: The device is running (not in
backup mode).
WKUP
Wake-Up Input
Input
VDDBU
Accept between 0V and
VDDBU.
ICE and JTAG
TCK
Test Clock
Input
VDDIOP0
No pull-up resistor, Schmitt
trigger
TDI Test Data In
Input
VDDIOP0
No pull-up resistor, Schmitt
trigger
TDO
Test Data Out
Output
VDDIOP0
TMS
Test Mode Select
Input
VDDIOP0
No pull-up resistor, Schmitt
trigger
JTAGSEL
JTAG Selection
Input
VDDBU
Pull-down resistor (15 kΩ).
RTCK
Return Test Clock
Output
VDDIOP0
Reset/Test
NRST
Microcontroller Reset (2)
Open drain output.
I/O Low VDDIOP0 Pull-Up resistor (100 kΩ),
Schmitt trigger
TST Test Mode Select
Input
VDDBU
Pull-down resistor (15 kΩ),
Schmitt trigger
NTRST
Test Reset Signal
Input
Pull-Up resistor (100 kΩ),
VDDIOP0
Schmitt trigger.
BMS
Boot Mode Select
Input
VDDIOP0
Must be connected to GND or
VDDIOP0.
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Debug Unit - DBGU
Input
Output
(1)
(1)
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input
Input
(1)
FIQ Fast Interrupt Input
Input
(1)
PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE
PA0 - PA31
Parallel IO Controller A
I/O
(1) Pulled-up input at reset
(100kΩ)(3), Schmitt trigger
PB0 - PB31
Parallel IO Controller B
I/O
(1) Pulled-up input at reset
(100kΩ)(3), Schmitt trigger
PC0 - PC31
Parallel IO Controller C
I/O
(1) Pulled-up input at reset
(100kΩ)(3), Schmitt trigger
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
5
5 Page 
4. Package and Pinout
The SAM9G45 is delivered in a 324-ball TFBGA package.
4.1 Mechanical Overview of the 324-ball TFBGA Package
Figure 4-1 shows the orientation of the 324-ball TFBGA Package
Figure 4-1. Orientation of the 324-ball TFBGA Package
Bottom VIEW
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAM9G45.PDF ] | |
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